> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Suraj > Kandpal > Sent: 15 November 2024 21:31 > To: intel-xe@xxxxxxxxxxxxxxxxxxxxx; intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Govindapillai, Vinod <vinod.govindapillai@xxxxxxxxx>; Nikula, Jani > <jani.nikula@xxxxxxxxx>; Kandpal, Suraj <suraj.kandpal@xxxxxxxxx> > Subject: [PATCH 5/6] drm/i915/display: Refactor DPKGC code to call it from > atomic_commit_tail > > Refactor the code to check the fixed refresh rate condition in the dpkgc > function itself and call it from intel_atomic_commit_tail so that we have all > the required values specially linetime which is computed after > intel_wm_compute, this will also help implement some WA's which requires > linetime. This also avoid writing into any of the registers while we are in > compute_config phase. > > Signed-off-by: Suraj Kandpal <suraj.kandpal@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_display.c | 2 ++ > drivers/gpu/drm/i915/display/skl_watermark.c | 27 +++++++++++--------- > drivers/gpu/drm/i915/display/skl_watermark.h | 1 + > 3 files changed, 18 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index e790a2de5b3d..d1880e0a5d29 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -7826,6 +7826,8 @@ static void intel_atomic_commit_tail(struct > intel_atomic_state *state) > /* Now enable the clocks, plane, pipe, and connectors that we set > up. */ > dev_priv->display.funcs.display->commit_modeset_enables(state); > > + intel_program_dpkgc_latency(state); > + > if (state->modeset) > intel_set_cdclk_post_plane_update(state); > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c > b/drivers/gpu/drm/i915/display/skl_watermark.c > index 2deb964daed3..0cc843314358 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > @@ -2854,17 +2854,28 @@ static int skl_wm_add_affected_planes(struct > intel_atomic_state *state, > * Program DEEP PKG_C_LATENCY Pkg C with all 1's. > * Program PKG_C_LATENCY Added Wake Time = 0 > */ > -static void > -skl_program_dpkgc_latency(struct drm_i915_private *i915, > - bool fixed_refresh_rate) > +void > +intel_program_dpkgc_latency(struct intel_atomic_state *state) > { > - struct intel_display *display = to_intel_display(&i915->drm); > + struct intel_display *display = to_intel_display(state); > + struct drm_i915_private *i915 = to_i915(display->drm); > + struct intel_crtc *crtc; > + struct intel_crtc_state *new_crtc_state; > u32 max_latency = LNL_PKG_C_LATENCY_MASK, added_wake_time = > 0; > u32 clear, val; > + bool fixed_refresh_rate = false; > + int i; > > if (DISPLAY_VER(display) < 20) > return; > > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > + if (!new_crtc_state->vrr.enable || > + (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax > && > + new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline)) > + fixed_refresh_rate = true; > + } > + > if (fixed_refresh_rate) { > max_latency = skl_watermark_max_latency(i915, 1); > if (max_latency == 0) > @@ -2886,7 +2897,6 @@ skl_compute_wm(struct intel_atomic_state *state) > struct intel_crtc *crtc; > struct intel_crtc_state __maybe_unused *new_crtc_state; > int ret, i; > - bool enable_dpkgc = false; > > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > ret = skl_build_pipe_wm(state, crtc); @@ -2911,15 +2921,8 > @@ skl_compute_wm(struct intel_atomic_state *state) > ret = skl_wm_add_affected_planes(state, crtc); > if (ret) > return ret; > - > - if ((new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax > && > - new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) > || > - !new_crtc_state->vrr.enable) > - enable_dpkgc = true; > } > > - skl_program_dpkgc_latency(to_i915(state->base.dev), > enable_dpkgc); > - Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@xxxxxxxxx> > skl_print_wm_changes(state); > > return 0; > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h > b/drivers/gpu/drm/i915/display/skl_watermark.h > index e73baec94873..35a1df7336e8 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.h > +++ b/drivers/gpu/drm/i915/display/skl_watermark.h > @@ -87,6 +87,7 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct > drm_i915_private *i915, > int ratio, bool joined_mbus); > void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state); > void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state); > +void intel_program_dpkgc_latency(struct intel_atomic_state *state); > > #endif /* __SKL_WATERMARK_H__ */ > > -- > 2.34.1