> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of
> Nemesa Garg
> Sent: Thursday, November 14, 2024 3:48 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; intel-xe@xxxxxxxxxxxxxxxxxxxxx
> Cc: Garg, Nemesa <nemesa.garg@xxxxxxxxx>
> Subject: [PATCH 5/5] drm/i915/display: Load the lut values and enable
> sharpness
>
> Load the lut values during pipe enable.
>
> v2: Add the display version check
> v3: Fix build issue
>
> Signed-off-by: Nemesa Garg <nemesa.garg@xxxxxxxxx>
Looks good to me.
Reviewed-by: Naga Venkata Srikanth V <nagavenkata.srikanth.v@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 3 +++
> drivers/gpu/drm/i915/display/intel_display.c | 6 ++++++
> .../gpu/drm/i915/display/intel_display_types.h | 2 ++
> drivers/gpu/drm/i915/display/skl_scaler.c | 15 ++++++++++++++-
> 4 files changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index a2c528d707f4..b4d7ae7b3db8 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -388,6 +388,9 @@ int intel_crtc_init(struct drm_i915_private *dev_priv,
> enum pipe pipe)
>
> drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) !=
> crtc->pipe);
>
> + if (DISPLAY_VER(dev_priv) >= 20)
> + drm_crtc_create_sharpness_strength_property(&crtc->base);
> +
> return 0;
>
> fail:
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f5e837310309..e81135f8daf9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1881,6 +1881,9 @@ static void hsw_crtc_enable(struct
> intel_atomic_state *state,
> intel_crtc_wait_for_next_vblank(wa_crtc);
> }
> }
> +
> + if (new_crtc_state->hw.casf_params.strength_changed)
> + intel_filter_lut_load(crtc, new_crtc_state);
> }
>
> void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) @@ -
> 7203,6 +7206,9 @@ static void intel_pre_update_crtc(struct
> intel_atomic_state *state,
> intel_vrr_set_transcoder_timings(new_crtc_state);
> }
>
> + if (intel_casf_strength_changed(state))
> + intel_casf_enable(new_crtc_state);
> +
> intel_fbc_update(state, crtc);
>
> drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915,
> POWER_DOMAIN_DC_OFF)); diff --git
> a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 19a671848f42..ad4138dcea8b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -920,6 +920,8 @@ struct intel_casf {
> struct scaler_filter_coeff coeff[SCALER_FILTER_NUM_TAPS];
> u8 win_size;
> bool need_scaler;
> + bool strength_changed;
> + u8 strength;
> };
>
> void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val); diff --git
> a/drivers/gpu/drm/i915/display/skl_scaler.c
> b/drivers/gpu/drm/i915/display/skl_scaler.c
> index 5311ef6c51d1..19f6cf62164c 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -7,6 +7,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_fb.h"
> +#include "intel_casf_regs.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
>
> @@ -869,12 +870,13 @@ void skl_scaler_get_config(struct intel_crtc_state
> *crtc_state)
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_crtc_scaler_state *scaler_state = &crtc_state-
> >scaler_state;
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> int id = -1;
> int i;
>
> /* find scaler attached to this pipe */
> for (i = 0; i < crtc->num_scalers; i++) {
> - u32 ctl, pos, size;
> + u32 ctl, pos, size, sharp;
>
> ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, i));
> if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) !=
> (PS_SCALER_EN | PS_BINDING_PIPE)) @@ -882,6 +884,17 @@ void
> skl_scaler_get_config(struct intel_crtc_state *crtc_state)
>
> id = i;
>
> + if (DISPLAY_VER(display) >= 20) {
> + sharp = intel_de_read(display,
> SHARPNESS_CTL(display, cpu_transcoder));
> + if (sharp & FILTER_EN) {
> + crtc_state->hw.casf_params.strength =
> +
> REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) - 16;
> + crtc_state->hw.casf_params.need_scaler =
> true;
> + crtc_state->hw.casf_params.win_size =
> + REG_FIELD_GET(FILTER_SIZE_MASK,
> sharp);
> + }
> + }
> +
> if (!crtc_state->hw.casf_params.need_scaler)
> crtc_state->pch_pfit.enabled = true;
>
> --
> 2.25.1
