In Xe3, hw can automatically switch to minimum / interim ddb allocations
for async flip use case. Configure the minimum and interim ddb
configurations. As usage of intel_display is recommended instead of
drm_i915_private, few preparatory patches were added for that purpose.
v2: Addressed review comments
Dropped few patches which do replacing i915 with intel_display
Dropped the debugfs patch to print dbuf allocation stats as
part of ddb info
Stanislav Lisovskiy (1):
drm/i915/xe3: Use hw support for min/interim ddb allocations for async
flip
Vinod Govindapillai (2):
drm/i915/display: update to plane_wm register access function
drm/i915/display: update to relative data rate handling
.../gpu/drm/i915/display/intel_atomic_plane.c | 27 +---
.../drm/i915/display/intel_display_types.h | 8 ++
.../drm/i915/display/skl_universal_plane.c | 26 ++++
.../i915/display/skl_universal_plane_regs.h | 15 ++
drivers/gpu/drm/i915/display/skl_watermark.c | 135 +++++++++++++-----
drivers/gpu/drm/i915/display/skl_watermark.h | 4 +
6 files changed, 160 insertions(+), 55 deletions(-)
--
2.34.1
