From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> The current approach of using non-posted DSB writes for the legacy LUT updats is causing CPU MMIO accesses to fail while the palette anti-collision logic is active. Try to avoid the problem by swithing to double posted writes and speeding up the update in other ways. Ville Syrjälä (4): drm/i915/dsb: Don't use indexed register writes needlessly drm/i915/color: Stop using non-posted DSB writes for legacy LUT drm/i915/dsb: Nuke the MMIO->indexed register write logic drm/i915: Do state check for color management changes drivers/gpu/drm/i915/display/intel_color.c | 81 ++++++++++++------- drivers/gpu/drm/i915/display/intel_dsb.c | 73 +++++++---------- drivers/gpu/drm/i915/display/intel_dsb.h | 2 + .../drm/i915/display/intel_modeset_verify.c | 2 + 4 files changed, 83 insertions(+), 75 deletions(-) -- 2.45.2
