On Tue, 19 Nov 2024, Imre Deak <imre.deak@xxxxxxxxx> wrote:
> On Mon, Nov 18, 2024 at 04:49:01PM +0200, Jani Nikula wrote:
>> Use the modern style for defining register contents. Expand the status
>> register contents a bit.
>>
>> TODO: The payload mapping fields have more bits on more recent
>> platforms.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 57 +++++++++++++++++----------------
>> 1 file changed, 30 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 7a35be56b7ef..9c198405349d 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3823,25 +3823,26 @@ enum skl_power_gate {
>> #define _TGL_DP_TP_CTL_A 0x60540
>> #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
>> #define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A)
>> -#define DP_TP_CTL_ENABLE (1 << 31)
>> -#define DP_TP_CTL_FEC_ENABLE (1 << 30)
>> -#define DP_TP_CTL_MODE_SST (0 << 27)
>> -#define DP_TP_CTL_MODE_MST (1 << 27)
>> -#define DP_TP_CTL_FORCE_ACT (1 << 25)
>> -#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
>> -#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A (0 << 19)
>> -#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B (1 << 19)
>> -#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C (2 << 19)
>> -#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
>> -#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
>> -#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
>> -#define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
>> -#define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
>> -#define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
>> -#define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
>> -#define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
>> -#define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
>> -#define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
>> +#define DP_TP_CTL_ENABLE REG_BIT(31)
>> +#define DP_TP_CTL_FEC_ENABLE REG_BIT(30)
>> +#define DP_TP_CTL_MODE_MASK REG_BIT(27)
>> +#define DP_TP_CTL_MODE_SST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 0)
>> +#define DP_TP_CTL_MODE_MST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 1)
>> +#define DP_TP_CTL_FORCE_ACT REG_BIT(25)
>> +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK REG_GENMASK(20, 19)
>> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 0)
>> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 1)
>> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 2)
>> +#define DP_TP_CTL_ENHANCED_FRAME_ENABLE REG_BIT(18)
>> +#define DP_TP_CTL_FDI_AUTOTRAIN REG_BIT(15)
>> +#define DP_TP_CTL_LINK_TRAIN_MASK REG_GENMASK(10, 8)
>> +#define DP_TP_CTL_LINK_TRAIN_PAT1 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 0)
>> +#define DP_TP_CTL_LINK_TRAIN_PAT2 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 1)
>> +#define DP_TP_CTL_LINK_TRAIN_PAT3 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 4)
>> +#define DP_TP_CTL_LINK_TRAIN_PAT4 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 5)
>> +#define DP_TP_CTL_LINK_TRAIN_IDLE REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 2)
>> +#define DP_TP_CTL_LINK_TRAIN_NORMAL REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 3)
>> +#define DP_TP_CTL_SCRAMBLE_DISABLE REG_BIT(7)
>>
>> /* DisplayPort Transport Status */
>> #define _DP_TP_STATUS_A 0x64044
>> @@ -3849,14 +3850,16 @@ enum skl_power_gate {
>> #define _TGL_DP_TP_STATUS_A 0x60544
>> #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
>> #define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A)
>> -#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
>> -#define DP_TP_STATUS_IDLE_DONE (1 << 25)
>> -#define DP_TP_STATUS_ACT_SENT (1 << 24)
>> -#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
>> -#define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
>> -#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
>> -#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
>> -#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
>> +#define DP_TP_STATUS_FEC_ENABLE_LIVE REG_BIT(28)
>> +#define DP_TP_STATUS_IDLE_DONE REG_BIT(25)
>> +#define DP_TP_STATUS_ACT_SENT REG_BIT(24)
>> +#define DP_TP_STATUS_MODE_STATUS_MST REG_BIT(23)
>> +#define DP_TP_STATUS_AUTOTRAIN_DONE REG_BIT(12)
>> +#define DP_TP_STATUS_STREAMS_ENABLED_MASK REG_GENMASK(21, 19)
>
> I assume the above is the 'Streams Enabled' field and that is bits 18:16
> on the platforms I checked. Bits 21:19 is 'DP Init Status'.
You're right. Good catch, thanks!
>
>> +#define DP_TP_STATUS_PAYLOAD_MAPPING_VC3_MASK REG_GENMASK(13, 12)
>> +#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2_MASK REG_GENMASK(9, 8)
>> +#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1_MASK REG_GENMASK(5, 4)
>> +#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0_MASK REG_GENMASK(1, 0)
>>
>> /* DDI Buffer Control */
>> #define _DDI_BUF_CTL_A 0x64000
>> --
>> 2.39.5
>>
--
Jani Nikula, Intel
