Read out the current plane configuration at init time into a new
plane_config structure. This allows us to track any existing
framebuffers attached to the plane and potentially re-use them in our
fbdev code for a smooth handoff.
Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/intel_display.c | 113 ++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_drv.h | 14 +++++
3 files changed, 128 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4377523..db6821a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -364,6 +364,7 @@ struct drm_i915_error_state {
};
struct intel_crtc_config;
+struct intel_plane_config;
struct intel_crtc;
struct intel_limit;
struct dpll;
@@ -402,6 +403,8 @@ struct drm_i915_display_funcs {
* fills out the pipe-config with the hw state. */
bool (*get_pipe_config)(struct intel_crtc *,
struct intel_crtc_config *);
+ void (*get_plane_config)(struct intel_crtc *,
+ struct intel_plane_config *);
int (*crtc_mode_set)(struct drm_crtc *crtc,
int x, int y,
struct drm_framebuffer *old_fb);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d4cc00c..c3c4fc3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2002,6 +2002,27 @@ unsigned long intel_gen4_compute_page_offset(int *x, int *y,
}
}
+int intel_format_to_fourcc(int format)
+{
+ switch (format) {
+ case DISPPLANE_8BPP:
+ return DRM_FORMAT_C8;
+ case DISPPLANE_BGRX555:
+ return DRM_FORMAT_ARGB1555;
+ case DISPPLANE_BGRX565:
+ return DRM_FORMAT_RGB565;
+ default:
+ case DISPPLANE_BGRX888:
+ return DRM_FORMAT_XRGB8888;
+ case DISPPLANE_RGBX888:
+ return DRM_FORMAT_XBGR8888;
+ case DISPPLANE_BGRX101010:
+ return DRM_FORMAT_XRGB2101010;
+ case DISPPLANE_RGBX101010:
+ return DRM_FORMAT_XBGR2101010;
+ }
+}
+
static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
int x, int y)
{
@@ -5463,6 +5484,81 @@ intel_framebuffer_pitch_for_width(int width, int bpp, bool tiled)
return ALIGN(pitch, 64);
}
+static void i9xx_get_plane_config(struct intel_crtc *crtc,
+ struct intel_plane_config *plane_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int pipe = crtc->pipe, plane = crtc->plane;
+ u32 val;
+
+ val = I915_READ(DSPCNTR(plane));
+
+ if (INTEL_INFO(dev)->gen >= 4)
+ if (val & DISPPLANE_TILED)
+ plane_config->tiled = true;
+
+ plane_config->pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
+
+ switch (plane_config->pixel_format) {
+ case DISPPLANE_8BPP:
+ case DISPPLANE_YUV422:
+ plane_config->bpp = 8;
+ break;
+ case DISPPLANE_BGRX555:
+ case DISPPLANE_BGRX565:
+ case DISPPLANE_BGRA555:
+ plane_config->bpp = 16;
+ break;
+ case DISPPLANE_BGRX888:
+ case DISPPLANE_BGRA888:
+ case DISPPLANE_RGBX888:
+ case DISPPLANE_RGBA888:
+ case DISPPLANE_RGBX101010:
+ case DISPPLANE_RGBA101010:
+ case DISPPLANE_BGRX101010:
+ plane_config->bpp = 32;
+ break;
+ }
+
+ if (INTEL_INFO(dev)->gen >= 4) {
+ if (plane_config->tiled)
+ plane_config->offset = I915_READ(DSPTILEOFF(plane));
+ else
+ plane_config->offset = I915_READ(DSPLINOFF(plane));
+ plane_config->base = I915_READ(DSPSURF(plane)) & 0xfffff000;
+ } else {
+ plane_config->base = I915_READ(DSPADDR(plane));
+ }
+
+ val = I915_READ(PIPESRC(pipe));
+ plane_config->pipe_width = ((val >> 16) & 0xfff) + 1;
+ plane_config->pipe_height = ((val >> 0) & 0xfff) + 1;
+
+ val = I915_READ(HTOTAL(pipe));
+ plane_config->fb_width = (val & 0xffff) + 1;
+ val = I915_READ(VTOTAL(pipe));
+ plane_config->fb_height = (val & 0xffff) + 1;
+
+ DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x\n",
+ pipe, plane, plane_config->fb_width,
+ plane_config->fb_height, plane_config->bpp,
+ plane_config->base);
+
+ plane_config->pitch =
+ intel_framebuffer_pitch_for_width(plane_config->fb_width,
+ plane_config->bpp,
+ plane_config->tiled);
+
+ plane_config->size = ALIGN(plane_config->pitch *
+ plane_config->fb_height, PAGE_SIZE);
+ plane_config->obj =
+ i915_gem_object_create_stolen_for_preallocated(dev,
+ plane_config->base,
+ plane_config->base,
+ plane_config->size);
+}
+
static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_config *pipe_config)
{
@@ -10523,6 +10619,7 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.update_plane = ironlake_update_plane;
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
+ dev_priv->display.get_plane_config = i9xx_get_plane_config;
dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
dev_priv->display.crtc_enable = valleyview_crtc_enable;
dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -10530,6 +10627,7 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.update_plane = i9xx_update_plane;
} else {
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
+ dev_priv->display.get_plane_config = i9xx_get_plane_config;
dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
dev_priv->display.crtc_enable = i9xx_crtc_enable;
dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -10798,6 +10896,7 @@ void intel_modeset_suspend_hw(struct drm_device *dev)
void intel_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *crtc;
int i, j, ret;
drm_mode_config_init(dev);
@@ -10854,6 +10953,18 @@ void intel_modeset_init(struct drm_device *dev)
/* Just in case the BIOS is doing something questionable. */
intel_disable_fbc(dev);
+
+ intel_modeset_setup_hw_state(dev, false);
+
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list,
+ base.head) {
+ if (!crtc->active)
+ continue;
+
+ if (dev_priv->display.get_plane_config)
+ dev_priv->display.get_plane_config(crtc,
+ &crtc->plane_config);
+ }
}
static void
@@ -11224,8 +11335,6 @@ void intel_modeset_gem_init(struct drm_device *dev)
intel_modeset_init_hw(dev);
intel_setup_overlay(dev);
-
- intel_modeset_setup_hw_state(dev, false);
}
void intel_modeset_cleanup(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b2d2cc1..cb72304 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -198,6 +198,18 @@ typedef struct dpll {
int p;
} intel_clock_t;
+struct intel_plane_config {
+ int pixel_format; /* DRM fourcc code */
+ int bpp;
+ bool tiled;
+ int base, offset;
+ int fb_width, fb_height;
+ int pipe_width, pipe_height;
+ int pitch;
+ int size;
+ struct drm_i915_gem_object *obj;
+};
+
struct intel_crtc_config {
/**
* quirks - bitfield with hw state readout quirks
@@ -347,6 +359,7 @@ struct intel_crtc {
bool cursor_visible;
struct intel_crtc_config config;
+ struct intel_plane_config plane_config;
uint32_t ddi_pll_sel;
@@ -696,6 +709,7 @@ void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc);
void intel_display_set_init_power(struct drm_device *dev, bool enable);
int valleyview_get_vco(struct drm_i915_private *dev_priv);
+int intel_format_to_fourcc(int format);
/* intel_dp.c */
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
--
1.8.4.2
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