On Mon, 2024-10-28 at 17:12 +0200, Ville Syrjälä wrote:
> On Thu, Oct 24, 2024 at 10:41:22AM +0000, Hogander, Jouni wrote:
> > On Wed, 2024-10-09 at 21:21 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > >
> > > Looks like CCS + async flips has been a thing for a while now.
> > > Enable this for TGL+ render compression modifiers.
> > >
> > > Note that we can't update AUX_DIST during async flips we must
> > > check to make sure it remains unchanged.
> > >
> > > We also can't do clear color. Supposedly there was some attempt
> > > to make it work, but apparently the issues only got ironed out
> > > in MTL. For now we'll not worry about it and refuse async flips
> > > with clear color modifiers.
> > >
> > > Bspec claims that media compression doesn't support async flips.
> > > Based on a quick test it does seem to work to some degree, but
> > > perhaps it has issues as well. Let's trust the spec here and
> > > continue to refuse async flips + media compression.
> >
> > Patch seems to be according to commit message. Could you please add
> > bspec references into commit message?
>
> That would be mostly: 49250,49251,49252,49253
With these bspec references added:
Reviewed-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
>
> >
> > BR,
> >
> > Jouni Högander
> >
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 14
> > > +++++++++++++-
> > > .../gpu/drm/i915/display/skl_universal_plane.c | 17 ++++++++++-
> > > ----
> > > --
> > > .../gpu/drm/i915/display/skl_universal_plane.h | 3 +++
> > > 3 files changed, 26 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index e1f6255e918b..21d412b158e8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -6512,6 +6512,9 @@ static int intel_async_flip_check_hw(struct
> > > intel_atomic_state *state, struct in
> > > case I915_FORMAT_MOD_Y_TILED:
> > > case I915_FORMAT_MOD_Yf_TILED:
> > > case I915_FORMAT_MOD_4_TILED:
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
> > > + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> > > case I915_FORMAT_MOD_4_TILED_BMG_CCS:
> > > case I915_FORMAT_MOD_4_TILED_LNL_CCS:
> > > break;
> > > @@ -6523,7 +6526,8 @@ static int intel_async_flip_check_hw(struct
> > > intel_atomic_state *state, struct in
> > > return -EINVAL;
> > > }
> > >
> > > - if (new_plane_state->hw.fb->format->num_planes >
> > > 1) {
> > > + if
> > > (intel_format_info_is_yuv_semiplanar(new_plane_state->hw.fb-
> > > >format,
> > > + new_plane
> > > _sta
> > > te->hw.fb->modifier)) {
> > > drm_dbg_kms(&i915->drm,
> > > "[PLANE:%d:%s] Planar formats
> > > do
> > > not support async flips\n",
> > > plane->base.base.id, plane-
> > > > base.name);
> > > @@ -6569,6 +6573,14 @@ static int
> > > intel_async_flip_check_hw(struct
> > > intel_atomic_state *state, struct in
> > > return -EINVAL;
> > > }
> > >
> > > + if (skl_plane_aux_dist(old_plane_state, 0) !=
> > > + skl_plane_aux_dist(new_plane_state, 0)) {
> > > + drm_dbg_kms(&i915->drm,
> > > + "[PLANE:%d:%s] AUX_DIST
> > > cannot be
> > > changed in async flip\n",
> > > + plane->base.base.id, plane-
> > > > base.name);
> > > + return -EINVAL;
> > > + }
> > > +
> > > if (!drm_rect_equals(&old_plane_state->uapi.src,
> > > &new_plane_state->uapi.src) ||
> > > !drm_rect_equals(&old_plane_state->uapi.dst,
> > > &new_plane_state->uapi.dst)) {
> > > drm_dbg_kms(&i915->drm,
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 9557b08ca2e2..0c09f76f8369 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -529,15 +529,18 @@ static u32 tgl_plane_min_alignment(struct
> > > intel_plane *plane,
> > > if (IS_ALDERLAKE_P(i915) &&
> > > HAS_ASYNC_FLIPS(i915))
> > > return mult * 16 * 1024;
> > > return mult * 4 * 1024;
> > > - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > - case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
> > > case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
> > > - case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
> > > case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> > > - case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> > > + if (IS_ALDERLAKE_P(i915) &&
> > > HAS_ASYNC_FLIPS(i915))
> > > + return mult * 16 * 1024;
> > > + fallthrough;
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > > + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
> > > case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
> > > + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> > > case I915_FORMAT_MOD_4_TILED_BMG_CCS:
> > > case I915_FORMAT_MOD_4_TILED_LNL_CCS:
> > > /*
> > > @@ -1192,8 +1195,8 @@ static u32 skl_plane_surf(const struct
> > > intel_plane_state *plane_state,
> > > return plane_surf;
> > > }
> > >
> > > -static u32 skl_plane_aux_dist(const struct intel_plane_state
> > > *plane_state,
> > > - int color_plane)
> > > +u32 skl_plane_aux_dist(const struct intel_plane_state
> > > *plane_state,
> > > + int color_plane)
> > > {
> > > struct drm_i915_private *i915 = to_i915(plane_state-
> > > > uapi.plane->dev);
> > > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > > b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > > index 541489479135..18b41d13f0bd 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > > @@ -37,4 +37,7 @@ bool icl_is_nv12_y_plane(struct
> > > drm_i915_private
> > > *dev_priv,
> > > u8 icl_hdr_plane_mask(void);
> > > bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum
> > > plane_id plane_id);
> > >
> > > +u32 skl_plane_aux_dist(const struct intel_plane_state
> > > *plane_state,
> > > + int color_plane);
> > > +
> > > #endif
> >
>
