Calculate WM0 prefill latency which accounts for maximum time
to fill data buffer up to watermark 0.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 21 ++++++++++++++++++++
drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index d3bbf335c749..8afa24943333 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2260,6 +2260,27 @@ static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
return wm0_lines;
}
+int skl_calc_wm0_prefill_latency(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ int cdclk_prefill_latency, wm0_prefill_latency;
+ int linetime =
+ DIV_ROUND_UP(crtc_state->hw.adjusted_mode.htotal * 1000,
+ crtc_state->hw.adjusted_mode.crtc_clock);
+ /*
+ * TODO: DIV_ROUND_UP will also round off to 1, so need to
+ * check upon if this can be eliminated here
+ */
+ cdclk_prefill_latency =
+ MIN(1, DIV_ROUND_UP(crtc_state->pixel_rate,
+ 2 * display->cdclk.hw.cdclk));
+ wm0_prefill_latency =
+ 20 + (linetime * skl_max_wm0_lines(crtc_state) * cdclk_prefill_latency);
+
+ return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
+ wm0_prefill_latency);
+}
+
static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
int wm0_lines)
{
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index e73baec94873..9495a142fbe5 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -23,6 +23,7 @@ struct skl_wm_level;
u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915);
+int skl_calc_wm0_prefill_latency(struct intel_crtc_state *crtc_state);
void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
void intel_sagv_post_plane_update(struct intel_atomic_state *state);
bool intel_can_enable_sagv(struct drm_i915_private *i915,
--
2.46.0
