From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> We determine the "spec" eDP power sequencing delays by refercing some max values from the eDP spec. Write out each number from the spec explicitly instead of precomputing the final number (that's the job of the computer). Makes it a bit easier to see what the supposed spec defined numbers actually are. Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_pps.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index ed52f84d4cf3..6946ba0004eb 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -1512,11 +1512,11 @@ static void pps_init_delays_spec(struct intel_dp *intel_dp, /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of * our hw here, which are all in 100usec. */ - spec->power_up = 210 * 10; /* T1+T3 */ + spec->power_up = (10 + 200) * 10; /* T1+T3 */ spec->backlight_on = 50 * 10; /* no limit for T8, use T7 instead */ spec->backlight_off = 50 * 10; /* no limit for T9, make it symmetric with T8 */ spec->power_down = 500 * 10; /* T10 */ - spec->power_cycle = 510 * 10; /* T11+T12 */ + spec->power_cycle = (10 + 500) * 10; /* T11+T12 */ intel_pps_dump_state(intel_dp, "spec", spec); } -- 2.45.2
