On 10/27/2024 7:15 PM, Ankit Nautiyal wrote:
For BMG 3 VDSC engines are supported and each pipe can then support 3 slices. For Ultra joiner cases for modes like 8k@120 Hz we require ultrajoiner and 3 x 4= 12 slices. Add support for 3 VDSC engines and 12 DSC slices. Rev2: Rebase Rev3: -Add patch to account for pixel replication in pipe_src. -Fix kernel test bot warning. -Minor refactoring. Rev4: -Address review comments from last version. -Add BW consideration with pixel replication -Split Odd pixel handling in separate patches. Rev 5: -Use num_streams instead of dsc_split. Rev 6: -Dropped patches for pixel replication and odd pixel removal. Ankit Nautiyal (7): drm/i915/dp: Update Comment for Valid DSC Slices per Line drm/i915/display: Prepare for dsc 3 stream splitter drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2 drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine drm/i915/dp: Ensure hactive is divisible by slice count drm/i915/dp: Enable 3 DSC engines for 12 slices
Pushed to drm-intel-next. Thanks for the reviews and comments. Regards, Ankit
drivers/gpu/drm/i915/display/icl_dsi.c | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 36 +++++++++++++++--- drivers/gpu/drm/i915/display/intel_vdsc.c | 38 +++++++++++++------ .../gpu/drm/i915/display/intel_vdsc_regs.h | 12 +++++- 6 files changed, 73 insertions(+), 21 deletions(-)
