In Xe3, hw can automatically switch to minimum / interim ddb allocations
for async flip use case. Configure the minimum and interim ddb
configurations. As usage of intel_display is recommended instead of
drm_i915_private, few preparatory patches were added for that purpose.
Stanislav Lisovskiy (1):
drm/i915/xe3: Use hw support for min/interim ddb allocations for async
flip
Vinod Govindapillai (7):
drm/i915/display: update intel_enabled_dbuf_slices_mask to use
intel_display
drm/i9i5/display: use intel_display in intel_de_read calls of
skl_watermark.c
drm/i915/display: update use_minimal_wm0_only to use intel_display
drm/i915/display: update use_min_ddb to use intel_display
drm/i915/display: update skl_plane_wm_equals to use intel_display
drm/i915/display: update to plane_wm register access function
drm/i915/debugfs: add dbuf alloc status as part of i915_ddb_info
.../gpu/drm/i915/display/intel_atomic_plane.c | 13 +-
.../drm/i915/display/intel_display_debugfs.c | 23 ++-
.../drm/i915/display/intel_display_power.c | 2 +-
.../i915/display/intel_display_power_well.c | 2 +-
.../drm/i915/display/intel_display_types.h | 8 +
.../drm/i915/display/skl_universal_plane.c | 31 ++++
.../i915/display/skl_universal_plane_regs.h | 14 ++
drivers/gpu/drm/i915/display/skl_watermark.c | 163 +++++++++++++-----
drivers/gpu/drm/i915/display/skl_watermark.h | 3 +-
9 files changed, 209 insertions(+), 50 deletions(-)
--
2.34.1
