On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Move intel_vdsc_min_cdclk() into intel_vdsc.c from intel_cdclk.c
> so that details about DSC are better contained.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 46 ----------------------
> drivers/gpu/drm/i915/display/intel_vdsc.c | 46 ++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vdsc.h | 1 +
> 3 files changed, 47 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index d376f7bccf21..9f38dd14b2d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -37,7 +37,6 @@
> #include "intel_cdclk.h"
> #include "intel_crtc.h"
> #include "intel_de.h"
> -#include "intel_dp.h"
> #include "intel_display_types.h"
> #include "intel_mchbar_regs.h"
> #include "intel_pci_config.h"
> @@ -2805,51 +2804,6 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
> return min_cdclk;
> }
>
> -static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
> -{
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct intel_display *display = to_intel_display(crtc);
> - int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> - int min_cdclk;
> -
> - if (!crtc_state->dsc.compression_enable)
> - return 0;
> -
> - /*
> - * When we decide to use only one VDSC engine, since
> - * each VDSC operates with 1 ppc throughput, pixel clock
> - * cannot be higher than the VDSC clock (cdclk)
> - * If there 2 VDSC engines, then pixel clock can't be higher than
> - * VDSC clock(cdclk) * 2 and so on.
> - */
> - min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances);
> -
> - if (crtc_state->joiner_pipes) {
> - int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
> -
> - /*
> - * According to Bigjoiner bw check:
> - * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
> - *
> - * We have already computed compressed_bpp, so now compute the min CDCLK that
> - * is required to support this compressed_bpp.
> - *
> - * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
> - *
> - * Since PPC = 2 with bigjoiner
> - * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
> - */
> - int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;
> - int min_cdclk_bj =
> - (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
> - pixel_clock) / (2 * bigjoiner_interface_bits);
> -
> - min_cdclk = max(min_cdclk, min_cdclk_bj);
> - }
> -
> - return min_cdclk;
> -}
> -
> int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> {
> int min_cdclk;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 40525f5c4c42..e6cb712373a9 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -14,6 +14,7 @@
> #include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> +#include "intel_dp.h"
> #include "intel_dsi.h"
> #include "intel_qp_tables.h"
> #include "intel_vdsc.h"
> @@ -1003,3 +1004,48 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent,
> intel_vdsc_dump_state(p, indent, crtc_state);
> drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
> }
> +
> +int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct intel_display *display = to_intel_display(crtc);
> + int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> + int min_cdclk;
> +
> + if (!crtc_state->dsc.compression_enable)
> + return 0;
> +
> + /*
> + * When we decide to use only one VDSC engine, since
> + * each VDSC operates with 1 ppc throughput, pixel clock
> + * cannot be higher than the VDSC clock (cdclk)
> + * If there 2 VDSC engines, then pixel clock can't be higher than
> + * VDSC clock(cdclk) * 2 and so on.
> + */
> + min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances);
> +
> + if (crtc_state->joiner_pipes) {
> + int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
> +
> + /*
> + * According to Bigjoiner bw check:
> + * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
> + *
> + * We have already computed compressed_bpp, so now compute the min CDCLK that
> + * is required to support this compressed_bpp.
> + *
> + * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
> + *
> + * Since PPC = 2 with bigjoiner
> + * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
> + */
> + int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;
> + int min_cdclk_bj =
> + (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
> + pixel_clock) / (2 * bigjoiner_interface_bits);
> +
> + min_cdclk = max(min_cdclk, min_cdclk_bj);
> + }
> +
> + return min_cdclk;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index 290b2e9b3482..9e2812f99dd7 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -31,5 +31,6 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void intel_vdsc_state_dump(struct drm_printer *p, int indent,
> const struct intel_crtc_state *crtc_state);
> +int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_VDSC_H__ */
--
Jani Nikula, Intel
