Re: [PATCH 2/3] drm/i915/psr: Change psr size limits check

["Nautiyal, Ankit K" <ankit.k.nautiyal@xxxxxxxxx>]

On 10/28/2024 6:14 PM, Nautiyal, Ankit K wrote:
> On 10/28/2024 1:13 PM, Suraj Kandpal wrote:
> > Change the check to only check for psr size limits till Pre-Xe2
> > since after that the psr size is equal to maximum pipe size anyways.
> >
> > --v2
> > -Check only size limit until pre-Xe2 [Matt]
> >
> > Bspec: 69885, 68858
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@xxxxxxxxx>
>
> LGTM.
>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
>
> > ---
> >   drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 4176163ec19a..7bc64eae9c8e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1453,11 +1453,11 @@ static bool intel_psr2_config_valid(struct 
> > intel_dp *intel_dp,
> >           return false;
> >       }
> >   -    if (DISPLAY_VER(display) >= 12) {

I think you missed to initialize psr_max_{h,v} and max_bpp with 
crtc_{h,v}display and crtc_state->pipe_bpp respectively.

Otherwise those are all 0's and will fail for Display ver > 14.


Regards,

Ankit

> > +    if (IS_DISPLAY_VER(display, 12, 14)) {
> >           psr_max_h = 5120;
> >           psr_max_v = 3200;
> >           max_bpp = 30;
> > -    } else if (DISPLAY_VER(display) >= 10) {
> > +    } else if (IS_DISPLAY_VER(display, 10, 11)) {
> >           psr_max_h = 4096;
> >           psr_max_v = 2304;
> >           max_bpp = 24;