On Fri, Nov 08, 2013 at 11:25:17AM +0200, Ville Syrjälä wrote: > On Thu, Nov 07, 2013 at 10:43:30AM +0800, Chon Ming Lee wrote: > > Some VLV PHY/PLL DPIO registers have group/lane/channel access. Current > > DPIO register definition doesn't have a structure way to break them > > down. As a result it is not easy to match the PHY/PLL registers with the > > configdb document. Rename those registers based on the configdb for easy > > cross references, and without the need to check the offset in the header > > file. > > > > New format is as following. > > > > <platform name>_<DPIO component><optional lane #>_DW<dword # in the > > doc>_<optional channel #> > > > > For example, > > > > VLV_PCS_DW0 - Group access to PCS for lane 0 to 3 for PCS DWORD 0. > > VLV_PCS01_DW0_CH0 - PCS access to lane 0/1, channel 0 for PCS DWORD 0. > > > > Another example is > > > > VLV_TX_DW0 - Group access to TX lane 0 to 3 for TX DWORD 0 > > VLV_TX0_DW0 - Refer to TX Lane 0 access only for TX DWORD 0. > > > > There is no functional change on this patch. > > > > v2: Rebase based on previous patch change. > > v3: There may be configdb different version that document the start DW > > differently. Add a comment to clarify. Fix up some mismatch start DW > > for second PLL block. (Ville) > > > > Suggested-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Signed-off-by: Chon Ming Lee <chon.ming.lee@xxxxxxxxx> > > Yeah looks good to me. > Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
