On Thu, Nov 07, 2013 at 10:43:30AM +0800, Chon Ming Lee wrote:
> Some VLV PHY/PLL DPIO registers have group/lane/channel access. Current
> DPIO register definition doesn't have a structure way to break them
> down. As a result it is not easy to match the PHY/PLL registers with the
> configdb document. Rename those registers based on the configdb for easy
> cross references, and without the need to check the offset in the header
> file.
>
> New format is as following.
>
> <platform name>_<DPIO component><optional lane #>_DW<dword # in the
> doc>_<optional channel #>
>
> For example,
>
> VLV_PCS_DW0 - Group access to PCS for lane 0 to 3 for PCS DWORD 0.
> VLV_PCS01_DW0_CH0 - PCS access to lane 0/1, channel 0 for PCS DWORD 0.
>
> Another example is
>
> VLV_TX_DW0 - Group access to TX lane 0 to 3 for TX DWORD 0
> VLV_TX0_DW0 - Refer to TX Lane 0 access only for TX DWORD 0.
>
> There is no functional change on this patch.
>
> v2: Rebase based on previous patch change.
> v3: There may be configdb different version that document the start DW
> differently. Add a comment to clarify. Fix up some mismatch start DW
> for second PLL block. (Ville)
>
> Suggested-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Chon Ming Lee <chon.ming.lee@xxxxxxxxx>
Yeah looks good to me.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 40 ++++----
> drivers/gpu/drm/i915/i915_reg.h | 191 ++++++++++++++++------------------
> drivers/gpu/drm/i915/intel_display.c | 48 ++++----
> drivers/gpu/drm/i915/intel_dp.c | 32 +++---
> drivers/gpu/drm/i915/intel_hdmi.c | 54 ++++------
> 5 files changed, 172 insertions(+), 193 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 7008aac..cae3e9c 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1650,28 +1650,28 @@ static int i915_dpio_info(struct seq_file *m, void *data)
>
> seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
>
> - seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
> - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A));
> - seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
> - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B));
> -
> - seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
> - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A));
> - seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
> - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B));
> -
> - seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
> - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A));
> - seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
> - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B));
> -
> - seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n",
> - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A));
> - seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n",
> - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B));
> + seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
> + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
> + seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
> + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
> +
> + seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
> + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
> + seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
> + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
> +
> + seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
> + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
> + seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
> + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
> +
> + seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
> + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
> + seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
> + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
>
> seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
> - vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE));
> + vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
>
> mutex_unlock(&dev_priv->dpio_lock);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 969ca2e..d06db23 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -452,18 +452,13 @@
> #define DPIO_SFR_BYPASS (1<<1)
> #define DPIO_CMNRST (1<<0)
>
> -#define _DPIO_TX3_SWING_CTL4_A 0x690
> -#define _DPIO_TX3_SWING_CTL4_B 0x2a90
> -#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX3_SWING_CTL4_A, \
> - _DPIO_TX3_SWING_CTL4_B)
> -
> #define DPIO_PHY(pipe) ((pipe) >> 1)
> #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
>
> /*
> * Per pipe/PLL DPIO regs
> */
> -#define _DPIO_DIV_A 0x800c
> +#define _VLV_PLL_DW3_CH0 0x800c
> #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
> #define DPIO_POST_DIV_DAC 0
> #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
> @@ -476,10 +471,10 @@
> #define DPIO_ENABLE_CALIBRATION (1<<11)
> #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
> #define DPIO_M2DIV_MASK 0xff
> -#define _DPIO_DIV_B 0x802c
> -#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
> +#define _VLV_PLL_DW3_CH1 0x802c
> +#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
>
> -#define _DPIO_REFSFR_A 0x8014
> +#define _VLV_PLL_DW5_CH0 0x8014
> #define DPIO_REFSEL_OVERRIDE 27
> #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
> #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
> @@ -487,118 +482,112 @@
> #define DPIO_PLL_REFCLK_SEL_MASK 3
> #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
> #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
> -#define _DPIO_REFSFR_B 0x8034
> -#define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
> +#define _VLV_PLL_DW5_CH1 0x8034
> +#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
>
> -#define _DPIO_CORE_CLK_A 0x801c
> -#define _DPIO_CORE_CLK_B 0x803c
> -#define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
> +#define _VLV_PLL_DW7_CH0 0x801c
> +#define _VLV_PLL_DW7_CH1 0x803c
> +#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
>
> -#define _DPIO_IREF_CTL_A 0x8040
> -#define _DPIO_IREF_CTL_B 0x8060
> -#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B)
> +#define _VLV_PLL_DW8_CH0 0x8040
> +#define _VLV_PLL_DW8_CH1 0x8060
> +#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
>
> -#define DPIO_IREF_BCAST 0xc044
> -#define _DPIO_IREF_A 0x8044
> -#define _DPIO_IREF_B 0x8064
> -#define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B)
> +#define VLV_PLL_DW9_BCAST 0xc044
> +#define _VLV_PLL_DW9_CH0 0x8044
> +#define _VLV_PLL_DW9_CH1 0x8064
> +#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
>
> -#define _DPIO_PLL_CML_A 0x804c
> -#define _DPIO_PLL_CML_B 0x806c
> -#define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B)
> +#define _VLV_PLL_DW10_CH0 0x8048
> +#define _VLV_PLL_DW10_CH1 0x8068
> +#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
>
> -#define _DPIO_LPF_COEFF_A 0x8048
> -#define _DPIO_LPF_COEFF_B 0x8068
> -#define DPIO_LPF_COEFF(pipe) _PIPE(pipe, _DPIO_LPF_COEFF_A, _DPIO_LPF_COEFF_B)
> +#define _VLV_PLL_DW11_CH0 0x804c
> +#define _VLV_PLL_DW11_CH1 0x806c
> +#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
>
> -#define DPIO_CALIBRATION 0x80ac
> +/* Spec for ref block start counts at DW10 */
> +#define VLV_REF_DW13 0x80ac
>
> -#define DPIO_FASTCLK_DISABLE 0x8100
> +#define VLV_CMN_DW0 0x8100
>
> /*
> * Per DDI channel DPIO regs
> */
>
> -#define _DPIO_PCS_TX_0 0x8200
> -#define _DPIO_PCS_TX_1 0x8400
> +#define _VLV_PCS_DW0_CH0 0x8200
> +#define _VLV_PCS_DW0_CH1 0x8400
> #define DPIO_PCS_TX_LANE2_RESET (1<<16)
> #define DPIO_PCS_TX_LANE1_RESET (1<<7)
> -#define DPIO_PCS_TX(port) _PORT(port, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1)
> +#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
>
> -#define _DPIO_PCS_CLK_0 0x8204
> -#define _DPIO_PCS_CLK_1 0x8404
> +#define _VLV_PCS_DW1_CH0 0x8204
> +#define _VLV_PCS_DW1_CH1 0x8404
> #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
> #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
> #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
> #define DPIO_PCS_CLK_SOFT_RESET (1<<5)
> -#define DPIO_PCS_CLK(port) _PORT(port, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1)
> -
> -#define _DPIO_PCS_CTL_OVR1_A 0x8224
> -#define _DPIO_PCS_CTL_OVR1_B 0x8424
> -#define DPIO_PCS_CTL_OVER1(port) _PORT(port, _DPIO_PCS_CTL_OVR1_A, \
> - _DPIO_PCS_CTL_OVR1_B)
> -
> -#define _DPIO_PCS_STAGGER0_A 0x822c
> -#define _DPIO_PCS_STAGGER0_B 0x842c
> -#define DPIO_PCS_STAGGER0(port) _PORT(port, _DPIO_PCS_STAGGER0_A, \
> - _DPIO_PCS_STAGGER0_B)
> -
> -#define _DPIO_PCS_STAGGER1_A 0x8230
> -#define _DPIO_PCS_STAGGER1_B 0x8430
> -#define DPIO_PCS_STAGGER1(port) _PORT(port, _DPIO_PCS_STAGGER1_A, \
> - _DPIO_PCS_STAGGER1_B)
> -
> -#define _DPIO_PCS_CLOCKBUF0_A 0x8238
> -#define _DPIO_PCS_CLOCKBUF0_B 0x8438
> -#define DPIO_PCS_CLOCKBUF0(port) _PORT(port, _DPIO_PCS_CLOCKBUF0_A, \
> - _DPIO_PCS_CLOCKBUF0_B)
> -
> -#define _DPIO_PCS_CLOCKBUF8_A 0x825c
> -#define _DPIO_PCS_CLOCKBUF8_B 0x845c
> -#define DPIO_PCS_CLOCKBUF8(port) _PORT(port, _DPIO_PCS_CLOCKBUF8_A, \
> - _DPIO_PCS_CLOCKBUF8_B)
> -
> -#define _DPIO_TX_SWING_CTL2_A 0x8288
> -#define _DPIO_TX_SWING_CTL2_B 0x8488
> -#define DPIO_TX_SWING_CTL2(port) _PORT(port, _DPIO_TX_SWING_CTL2_A, \
> - _DPIO_TX_SWING_CTL2_B)
> -
> -#define _DPIO_TX_SWING_CTL3_A 0x828c
> -#define _DPIO_TX_SWING_CTL3_B 0x848c
> -#define DPIO_TX_SWING_CTL3(port) _PORT(port, _DPIO_TX_SWING_CTL3_A, \
> - _DPIO_TX_SWING_CTL3_B)
> -
> -#define _DPIO_TX_SWING_CTL4_A 0x8290
> -#define _DPIO_TX_SWING_CTL4_B 0x8490
> -#define DPIO_TX_SWING_CTL4(port) _PORT(port, _DPIO_TX_SWING_CTL4_A, \
> - _DPIO_TX_SWING_CTL4_B)
> -
> -#define _DPIO_TX_OCALINIT_0 0x8294
> -#define _DPIO_TX_OCALINIT_1 0x8494
> +#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
> +
> +#define _VLV_PCS_DW8_CH0 0x8220
> +#define _VLV_PCS_DW8_CH1 0x8420
> +#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
> +
> +#define _VLV_PCS01_DW8_CH0 0x0220
> +#define _VLV_PCS23_DW8_CH0 0x0420
> +#define _VLV_PCS01_DW8_CH1 0x2620
> +#define _VLV_PCS23_DW8_CH1 0x2820
> +#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
> +#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
> +
> +#define _VLV_PCS_DW9_CH0 0x8224
> +#define _VLV_PCS_DW9_CH1 0x8424
> +#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
> +
> +#define _VLV_PCS_DW11_CH0 0x822c
> +#define _VLV_PCS_DW11_CH1 0x842c
> +#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
> +
> +#define _VLV_PCS_DW12_CH0 0x8230
> +#define _VLV_PCS_DW12_CH1 0x8430
> +#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
> +
> +#define _VLV_PCS_DW14_CH0 0x8238
> +#define _VLV_PCS_DW14_CH1 0x8438
> +#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
> +
> +#define _VLV_PCS_DW23_CH0 0x825c
> +#define _VLV_PCS_DW23_CH1 0x845c
> +#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
> +
> +#define _VLV_TX_DW2_CH0 0x8288
> +#define _VLV_TX_DW2_CH1 0x8488
> +#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
> +
> +#define _VLV_TX_DW3_CH0 0x828c
> +#define _VLV_TX_DW3_CH1 0x848c
> +#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
> +
> +#define _VLV_TX_DW4_CH0 0x8290
> +#define _VLV_TX_DW4_CH1 0x8490
> +#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
> +
> +#define _VLV_TX3_DW4_CH0 0x690
> +#define _VLV_TX3_DW4_CH1 0x2a90
> +#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
> +
> +#define _VLV_TX_DW5_CH0 0x8294
> +#define _VLV_TX_DW5_CH1 0x8494
> #define DPIO_TX_OCALINIT_EN (1<<31)
> -#define DPIO_TX_OCALINIT(port) _PORT(port, _DPIO_TX_OCALINIT_0, \
> - _DPIO_TX_OCALINIT_1)
> -
> -#define _DPIO_TX_CTL_0 0x82ac
> -#define _DPIO_TX_CTL_1 0x84ac
> -#define DPIO_TX_CTL(port) _PORT(port, _DPIO_TX_CTL_0, _DPIO_TX_CTL_1)
> -
> -#define _DPIO_TX_LANE_0 0x82b8
> -#define _DPIO_TX_LANE_1 0x84b8
> -#define DPIO_TX_LANE(port) _PORT(port, _DPIO_TX_LANE_0, _DPIO_TX_LANE_1)
> -
> -#define _DPIO_DATA_CHANNEL1 0x8220
> -#define _DPIO_DATA_CHANNEL2 0x8420
> -#define DPIO_DATA_CHANNEL(port) _PORT(port, _DPIO_DATA_CHANNEL1, _DPIO_DATA_CHANNEL2)
> -
> -#define _DPIO_PORT0_PCS0 0x0220
> -#define _DPIO_PORT0_PCS1 0x0420
> -#define _DPIO_PORT1_PCS2 0x2620
> -#define _DPIO_PORT1_PCS3 0x2820
> -#define DPIO_DATA_LANE_A(port) _PORT(port, _DPIO_PORT0_PCS0, _DPIO_PORT1_PCS2)
> -#define DPIO_DATA_LANE_B(port) _PORT(port, _DPIO_PORT0_PCS1, _DPIO_PORT1_PCS3)
> -#define DPIO_DATA_CHANNEL1 0x8220
> -#define DPIO_DATA_CHANNEL2 0x8420
> +#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
> +
> +#define _VLV_TX_DW11_CH0 0x82ac
> +#define _VLV_TX_DW11_CH1 0x84ac
> +#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
> +
> +#define _VLV_TX_DW14_CH0 0x82b8
> +#define _VLV_TX_DW14_CH1 0x84b8
> +#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
>
> /*
> * Fence registers
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b1d20b6..e1197ee 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4794,24 +4794,24 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
> * PLLB opamp always calibrates to max value of 0x3f, force enable it
> * and set it to a reasonable value instead.
> */
> - reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
> + reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
> reg_val &= 0xffffff00;
> reg_val |= 0x00000030;
> - vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
> + vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
>
> - reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
> + reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
> reg_val &= 0x8cffffff;
> reg_val = 0x8c000000;
> - vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
> + vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
>
> - reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
> + reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
> reg_val &= 0xffffff00;
> - vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
> + vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
>
> - reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
> + reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
> reg_val &= 0x00ffffff;
> reg_val |= 0xb0000000;
> - vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
> + vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
> }
>
> static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
> @@ -4880,15 +4880,15 @@ static void vlv_update_pll(struct intel_crtc *crtc)
> vlv_pllb_recal_opamp(dev_priv, pipe);
>
> /* Set up Tx target for periodic Rcomp update */
> - vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
> + vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
>
> /* Disable target IRef on PLL */
> - reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
> + reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
> reg_val &= 0x00ffffff;
> - vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
> + vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
>
> /* Disable fast lock */
> - vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
> + vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
>
> /* Set idtafcrecal before PLL is enabled */
> mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
> @@ -4902,48 +4902,48 @@ static void vlv_update_pll(struct intel_crtc *crtc)
> * Note: don't use the DAC post divider as it seems unstable.
> */
> mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
> - vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
> + vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
>
> mdiv |= DPIO_ENABLE_CALIBRATION;
> - vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
> + vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
>
> /* Set HBR and RBR LPF coefficients */
> if (crtc->config.port_clock == 162000 ||
> intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
> intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
> - vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
> + vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
> 0x009f0003);
> else
> - vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
> + vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
> 0x00d0000f);
>
> if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
> intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
> /* Use SSC source */
> if (!pipe)
> - vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
> + vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
> 0x0df40000);
> else
> - vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
> + vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
> 0x0df70000);
> } else { /* HDMI or VGA */
> /* Use bend source */
> if (!pipe)
> - vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
> + vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
> 0x0df70000);
> else
> - vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
> + vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
> 0x0df40000);
> }
>
> - coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
> + coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
> coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
> if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
> intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
> coreclk |= 0x01000000;
> - vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
> + vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
>
> - vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
> + vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
>
> /* Enable DPIO clock input */
> dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
> @@ -5421,7 +5421,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
> int refclk = 100000;
>
> mutex_lock(&dev_priv->dpio_lock);
> - mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
> + mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
> mutex_unlock(&dev_priv->dpio_lock);
>
> clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index aea9e28..558cb54 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1846,16 +1846,16 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
>
> mutex_lock(&dev_priv->dpio_lock);
>
> - val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
> val = 0;
> if (pipe)
> val |= (1<<21);
> else
> val &= ~(1<<21);
> val |= 0x001000c4;
> - vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
>
> mutex_unlock(&dev_priv->dpio_lock);
>
> @@ -1881,19 +1881,19 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
>
> /* Program Tx lane resets to default */
> mutex_lock(&dev_priv->dpio_lock);
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
> DPIO_PCS_TX_LANE2_RESET |
> DPIO_PCS_TX_LANE1_RESET);
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
> DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
> DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
> (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
> DPIO_PCS_CLK_SOFT_RESET);
>
> /* Fix up inter-pair skew failure */
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
> mutex_unlock(&dev_priv->dpio_lock);
> }
>
> @@ -2110,14 +2110,14 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
> }
>
> mutex_lock(&dev_priv->dpio_lock);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> uniqtranscale_reg_value);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
> mutex_unlock(&dev_priv->dpio_lock);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index eeaf533..61cff67 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1090,36 +1090,28 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
>
> /* Enable clock channels for this port */
> mutex_lock(&dev_priv->dpio_lock);
> - val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
> val = 0;
> if (pipe)
> val |= (1<<21);
> else
> val &= ~(1<<21);
> val |= 0x001000c4;
> - vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
>
> /* HDMI 1.0V-2dB */
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port),
> - 0x2b245f5f);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
> - 0x5578b83a);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port),
> - 0x0c782040);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX3_SWING_CTL4(port),
> - 0x2b247878);
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port),
> - 0x00002000);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port),
> - DPIO_TX_OCALINIT_EN);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
>
> /* Program lane clock */
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port),
> - 0x00760018);
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port),
> - 0x00400888);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
> mutex_unlock(&dev_priv->dpio_lock);
>
> intel_enable_hdmi(encoder);
> @@ -1142,24 +1134,22 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>
> /* Program Tx lane resets to default */
> mutex_lock(&dev_priv->dpio_lock);
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
> DPIO_PCS_TX_LANE2_RESET |
> DPIO_PCS_TX_LANE1_RESET);
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
> DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
> DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
> (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
> DPIO_PCS_CLK_SOFT_RESET);
>
> /* Fix up inter-pair skew failure */
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
> -
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port),
> - 0x00002000);
> - vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port),
> - DPIO_TX_OCALINIT_EN);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
> +
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
> + vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> mutex_unlock(&dev_priv->dpio_lock);
> }
>
> @@ -1174,8 +1164,8 @@ static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
>
> /* Reset lanes to avoid HDMI flicker (VLV w/a) */
> mutex_lock(&dev_priv->dpio_lock);
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), 0x00000000);
> - vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port), 0x00e00060);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
> mutex_unlock(&dev_priv->dpio_lock);
> }
>
> --
> 1.7.7.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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