Hi Dave,
So here's the Broadwell pull request. From a kernel driver pov there's
two areas with big changes in Broadwell:
- Completely new enumerated interrupt bits. On the plus side it now looks
fairly unform and sane.
- Completely new pagetable layout.
To ensure minimal impact on existing platforms we've refactored both the
irq and low-level gtt handling code a lot in anticipation of the bdw push.
So now bdw enabling in these areas just plugs in a bunch of vfuncs.
Otherwise it's all fairly harmless adjusting of switch cases and
if-ladders to shovel bdw into the right blocks. So minimized impact on
existing platforms. I've also merged the bdw-stage1 branch into our
-nightly integration branch for the past week to make sure we don't break
anything.
Note that there's still quite a flurry or patches floating around, but
I've figured I'll push this out. I plan to keep the bdw fixes separate
from my usual -fixes stream so that you can reject them easily in case it
still looks like too much churn. Also, bdw is for now hidden behind the
preliminary hw enabling module option. So there's no real pressure to get
follow-up patches all into 3.13.
Cheers, Daniel
PS: Last minute rebase was to quench a bisect fail since I've fumbled
squashing in some of the bugfixes from yesterday. Hence the -v2 tag.
The following changes since commit 7f16e5c1416070dc590dd333a2d677700046a4ab:
Merge tag 'v3.12' into drm-intel-next (2013-11-04 16:28:52 +0100)
are available in the git repository at:
git://people.freedesktop.org/~danvet/drm-intel tags/bdw-stage1-2013-11-08-v2
for you to fetch changes up to 13b3a0a77625c09c84825ef6ba81d957ec207841:
drm/i915: Mask the vblank interrupt on bdw by default (2013-11-08 18:10:14 +0100)
----------------------------------------------------------------
Art Runyan (1):
drm/i915/bdw: Add BDW DDI buffer translation values
Ben Widawsky (46):
drm/i915/bdw: IS_GEN8 definition
drm/i915/bdw: Handle forcewake for writes on gen8
drm/i915/bdw: Initialize BDW forcewake vfuncs
drm/i915/bdw: Add device IDs
drm/i915/bdw: Fences on gen8 look just like gen7
drm/i915/bdw: Swizzling support
drm/i915/bdw: HW context support
drm/i915/bdw: Clock gating init
drm/i915/bdw: display stuff
drm/i915/bdw: support GMS and GGMS changes
drm/i915/bdw: Implement interrupt changes
drm/i915/bdw: Add interrupt info to debugfs
drm/i915/bdw: Support 64b relocations
drm/i915/bdw: dispatch updates (64b related)
drm/i915/bdw: Update MI_FLUSH_DW
drm/i915/bdw: debugfs updates
drm/i915/bdw: Update relevant error state
drm/i915/bdw: Make gen8_gmch_probe
drm/i915/bdw: Create gen8_gtt_pte_t
drm/i915/bdw: Add GTT functions
drm/i915/bdw: Support BDW caching
drm/i915/bdw: PPGTT init & cleanup
drm/i915/bdw: Initialize the PDEs
drm/i915/bdw: Implement PPGTT clear range
drm/i915/bdw: Implement PPGTT insert
drm/i915/bdw: Implement PPGTT enable
drm/i915/bdw: unleash PPGTT
drm/i915/bdw: Render ring flushing
drm/i915/bdw: ppgtt info in debugfs
drm/i915/bdw: BSD init for gen8 also
drm/i915/bdw: Implement WaSwitchSolVfFArbitrationPriority
drm/i915/bdw: Use The GT mailbox for IPS enable/disable
drm/i915/bdw: Support eDP PSR
drm/i915/bdw: Use HSW formula for ring freq scaling
drm/i915/bdw: Don't wait for c0 threads on forcewake
drm/i915/bdw: Create a separate BDW rps enable
drm/i915/bdw: Disable semaphores
drm/i915/bdw: Implement edp PSR workarounds
drm/i915/bdw: BWGTLB clock gate disable
ddrm/i915/bdw: Disable centroid pixel perf optimization
drm/i915/bdw: Sampler power bypass disable
drm/i915/bdw: Limit SDE poly depth FIFO to 2
drm/i915/bdw: conservative SBE VUE cache mode
drm/i915/bdw: WaSingleSubspanDispatchOnAALinesAndPoints
drm/i915/bdw: Change dp aux timeout to 600us on DDIA
drm/i915/bdw: Add BDW PCH check first
Damien Lespiau (2):
drm/i915/bdw: Broadwell has 3 pipes
drm/i915/bdw: Broadwell has a max port clock of 300Mhz on HDMI
Daniel Vetter (10):
drm/i915/bdw: Disable PPGTT for now
drm/i915/bdw: Take render error interrupt out of the mask
drm/i915: Optimize pipe irq handling on bdw
drm/i915: Fix up the bdw pipe interrupt enable lists
drm/i915: Wire up port A aux channel
drm/i915: Wire up PCH interrupts for bdw
drm/i915: Wire up pipe CRC support for bdw
drm/i915: Optimize gen8_enable|disable_vblank functions
drm/i915: Wire up cpu fifo underrun reporting support for bdw
drm/i915: Mask the vblank interrupt on bdw by default
Paulo Zanoni (11):
drm/i915/bdw: add IS_BROADWELL macro
drm/i915/bdw: add Broadwell sprite/plane/cursor checks
drm/i915/bdw: Broadwell also has the "power down well"
drm/i915/bdw: pretend we have LPT LP on Broadwell
drm/i915/bdw: on Broadwell, the panel fitter is on the pipe
drm/i915/bdw: Broadwell has PIPEMISC
drm/i915/bdw: get the correct LCPLL frequency on Broadwell
drm/i915/bdw: add BDW DDI buf translations for eDP
drm/i915/bdw: add support for BDW DP voltage swings and pre-emphasis
drm/i915/bdw: BDW also has only 2 FDI lanes
drm/i915/bdw: check DPD on port D when setting the DDI buffers
Ville Syrjälä (5):
drm/i915/bdw: Don't muck with gtt_size on Gen8 when PPGTT setup fails
drm/i915/bdw: Use pipe CSC on Broadwell
drm/i915/bdw: Add Broadwell display FIFO limits
drm/i915/bdw: Enable trickle feed on Broadwell
drm/i915: Use hsw_crt_get_config on BDW
arch/x86/kernel/early-quirks.c | 12 +
drivers/gpu/drm/i915/i915_debugfs.c | 109 ++++++-
drivers/gpu/drm/i915/i915_drv.c | 34 +-
drivers/gpu/drm/i915/i915_drv.h | 36 ++-
drivers/gpu/drm/i915/i915_gem.c | 3 +
drivers/gpu/drm/i915/i915_gem_context.c | 3 +
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 35 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 504 +++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +
drivers/gpu/drm/i915/i915_irq.c | 375 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 123 ++++++-
drivers/gpu/drm/i915/intel_crt.c | 11 +-
drivers/gpu/drm/i915/intel_ddi.c | 124 ++++++-
drivers/gpu/drm/i915/intel_display.c | 82 +++--
drivers/gpu/drm/i915/intel_dp.c | 66 +++-
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 164 +++++++++-
drivers/gpu/drm/i915/intel_ringbuffer.c | 194 ++++++++++-
drivers/gpu/drm/i915/intel_sprite.c | 7 +-
drivers/gpu/drm/i915/intel_uncore.c | 58 +++-
include/drm/i915_drm.h | 4 +
include/drm/i915_pciids.h | 25 ++
22 files changed, 1847 insertions(+), 126 deletions(-)
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
