== Series Details == Series: Add support for 3 VDSC engines 12 slices (rev5) URL : https://patchwork.freedesktop.org/series/139934/ State : warning == Summary == Error: dim checkpatch failed e10dc647dab1 drm/i915/dp: Update Comment for Valid DSC Slices per Line 9b62b6dbf1b1 drm/i915/display: Prepare for dsc 3 stream splitter b648dfb4f350 drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine 62425f3c6ba2 drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2 f6c807b6d7aa drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine 80b3cac8f820 drm/i915/dp: Ensure hactive is divisible by slice count bae1bb5875d9 drm/i915/dp: Enable 3 DSC engines for 12 slices 7998440e6a13 drm/i915/display: Add macro HAS_PIXEL_REPLICATION -:19: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #19: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:152: +#define HAS_PIXEL_REPLICATION(i915) (HAS_DSC(i915) && \ + (DISPLAY_VER(i915) >= 20 || \ + DISPLAY_VER_FULL(i915) == IP_VER(14, 1))) total: 0 errors, 0 warnings, 1 checks, 9 lines checked bd77528aa771 drm/i915/display: Add support for DSC pixel replication -:141: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #141: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:59: +#define DSC_PIXEL_REPLICATION(count) (REG_FIELD_PREP(DSC_PIXEL_REPLICATION_MASK, (count))) total: 0 errors, 1 warnings, 0 checks, 101 lines checked 823e0adb2157 drm/i915/dp_mst: Account for pixel replication for MST overhead with DSC 46400fe947b0 drm/i915/dp: Account for pixel replication for BW computation with DSC 22df068f09ce drm/i915/display: Account for pixel replication in pipe_src f0ce2acbe274 drm/i915/dp: Enable DSC pixel replication 55336aa227e5 drm/i915/dsc: Introduce odd pixel removal 0350b3583749 drm/i915/display: Adjust Pipe SRC Width for Odd Pixels 705832d27ba2 drm/i915/dp: Add Check for Odd Pixel Requirement
