On Wed, 16 Oct 2024, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Gen2/3 pfit doesn't support downscaling at all, so reject it.
>
> On i965+ downscaling is supported by the hardware (max scale
> factor < 2.0), but as downscaling increases the effective
> pixel rate we can't safely allow it unless
> intel_crtc_compute_pixel_rate() gets fixed. Probably the
> best solution would be to calculate (at least an
> apporiximate) pfit destination window and use
> ilk_pipe_pixel_rate() for all platforms. For now reject
> downscaling on all gmch platforms.
>
> The intel ddx has a similar check for this in userspace,
> modesetting ddx does not. And presumably wayland compositors
> also do not make such assumptions in userspace.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Acked-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_panel.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
> index fb7def772376..89cac3b3fd02 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -681,6 +681,7 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
> static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
> @@ -693,6 +694,25 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
> adjusted_mode->crtc_vdisplay == pipe_src_h)
> goto out;
>
> + /*
> + * TODO: implement downscaling for i965+. Need to account
> + * for downscaling in intel_crtc_compute_pixel_rate().
> + */
> + if (adjusted_mode->crtc_hdisplay < pipe_src_w) {
> + drm_dbg_kms(display->drm,
> + "[CRTC:%d:%s] pfit horizontal downscaling (%d->%d) not supported\n",
> + crtc->base.base.id, crtc->base.name,
> + pipe_src_w, adjusted_mode->crtc_hdisplay);
> + return -EINVAL;
> + }
> + if (adjusted_mode->crtc_vdisplay < pipe_src_h) {
> + drm_dbg_kms(display->drm,
> + "[CRTC:%d:%s] pfit vertical downscaling (%d->%d) not supported\n",
> + crtc->base.base.id, crtc->base.name,
> + pipe_src_h, adjusted_mode->crtc_vdisplay);
> + return -EINVAL;
> + }
> +
> switch (conn_state->scaling_mode) {
> case DRM_MODE_SCALE_CENTER:
> /*
--
Jani Nikula, Intel
