> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@xxxxxxxxx>
> Sent: Thursday, October 17, 2024 1:54 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: intel-xe@xxxxxxxxxxxxxxxxxxxxx; Kandpal, Suraj
> <suraj.kandpal@xxxxxxxxx>
> Subject: [PATCH 03/10] drm/i915/vdsc: Add register bits for VDSC2 engine
>
> Add bits to enable third VDSC engine VDSC2.
The subject and commit message dont entirely do justice to what is being done in the patch.
You are also adding definitions, and adding prospect for get_config and enabling dsc with 3 engines
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_vdsc.c | 21 +++++++++++++++----
> .../gpu/drm/i915/display/intel_vdsc_regs.h | 4 ++++
> 3 files changed, 22 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8bd63da8516c..e6d37d28c5c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -912,6 +912,7 @@ struct intel_csc_matrix { enum intel_dsc_split_state {
> INTEL_DSC_SPLIT_DISABLED,
> INTEL_DSC_SPLIT_2_STREAMS,
> + INTEL_DSC_SPLIT_3_STREAMS,
> };
This and the below name changes can be avoided if we make dsc_split a int no_dsc_spilt_streams
Regards,
Suraj Kandpal
>
> void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val); diff --git
> a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index bc5f8c5cb1d4..e34483d5be36 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -380,6 +380,8 @@ intel_dsc_power_domain(struct intel_crtc *crtc,
> enum transcoder cpu_transcoder) static int
> intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state) {
> switch (crtc_state->dsc.dsc_split) {
> + case INTEL_DSC_SPLIT_3_STREAMS:
> + return 3;
> case INTEL_DSC_SPLIT_2_STREAMS:
> return 2;
> case INTEL_DSC_SPLIT_DISABLED:
> @@ -782,6 +784,12 @@ void intel_dsc_enable(const struct intel_crtc_state
> *crtc_state)
> dss_ctl2_val |= VDSC1_ENABLE;
> dss_ctl1_val |= JOINER_ENABLE;
> }
> +
> + if (vdsc_instances_per_pipe > 2) {
> + dss_ctl2_val |= VDSC2_ENABLE;
> + dss_ctl2_val |= SMALL_JOINER_CONFIG_3_ENGINES;
> + }
> +
> if (crtc_state->joiner_pipes) {
> if (intel_crtc_ultrajoiner_enable_needed(crtc_state))
> dss_ctl1_val |= ULTRA_JOINER_ENABLE; @@ -983,11
> +991,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> if (!crtc_state->dsc.compression_enable)
> goto out;
>
> - if ((dss_ctl1 & JOINER_ENABLE) &&
> - (dss_ctl2 & VDSC1_ENABLE))
> - crtc_state->dsc.dsc_split = INTEL_DSC_SPLIT_2_STREAMS;
> - else
> + if (dss_ctl1 & JOINER_ENABLE) {
> + if (dss_ctl2 & (VDSC2_ENABLE |
> SMALL_JOINER_CONFIG_3_ENGINES))
> + crtc_state->dsc.dsc_split =
> INTEL_DSC_SPLIT_3_STREAMS;
> +
> + else if (dss_ctl2 & VDSC1_ENABLE)
> + crtc_state->dsc.dsc_split =
> INTEL_DSC_SPLIT_2_STREAMS;
> + } else {
> crtc_state->dsc.dsc_split = INTEL_DSC_SPLIT_DISABLED;
> + }
>
> intel_dsc_get_pps_config(crtc_state);
> out:
> @@ -997,6 +1009,7 @@ void intel_dsc_get_config(struct intel_crtc_state
> *crtc_state) static const char * const dsc_split_str[] = {
> [INTEL_DSC_SPLIT_DISABLED] = "DISABLED",
> [INTEL_DSC_SPLIT_2_STREAMS] = "2 STREAMS",
> + [INTEL_DSC_SPLIT_3_STREAMS] = "3 STREAMS",
> };
>
> static const char *dsc_split_name(enum intel_dsc_split_state dsc_split) diff
> --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> index d7a72b95ee7e..941f4ff6b940 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> @@ -22,6 +22,10 @@
>
> #define DSS_CTL2 _MMIO(0x67404)
> #define VDSC0_ENABLE REG_BIT(31)
> +#define VDSC2_ENABLE REG_BIT(30)
> +#define SMALL_JOINER_CONFIG_3_ENGINES REG_BIT(23)
> +#define ODD_PIXEL_REMOVAL REG_BIT(18)
> +#define ODD_PIXEL_REMOVAL_CONFIG_EOL REG_BIT(17)
> #define VDSC1_ENABLE REG_BIT(15)
> #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> --
> 2.45.2
