We only support resolution up to 4k for single pipe when using
YUV420 format so we prune these modes and restrict the plane size
at src.
Signed-off-by: Suraj Kandpal <suraj.kandpal@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 ++++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6cdc968522df..1823b509cbfb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1374,6 +1374,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
{
struct intel_connector *connector = to_intel_connector(_connector);
struct intel_dp *intel_dp = intel_attached_dp(connector);
+ enum intel_output_format sink_format;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
const struct drm_display_mode *fixed_mode;
int target_clock = mode->clock;
@@ -1408,6 +1409,11 @@ intel_dp_mode_valid(struct drm_connector *_connector,
mode->hdisplay, target_clock);
max_dotclk *= num_joined_pipes;
+ sink_format = intel_dp_sink_format(connector, mode);
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
+ mode->hdisplay > 4096)
+ return MODE_NO_420;
+
if (target_clock > max_dotclk)
return MODE_CLOCK_HIGH;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 4dec9e693218..5b1f6069e5da 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -435,7 +435,10 @@ static int xe3_plane_max_width(const struct drm_framebuffer *fb,
int color_plane,
unsigned int rotation)
{
- return 6144;
+ if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
+ return 4096;
+ else
+ return 6144;
}
static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb,
--
2.47.0
