> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Vinod
> Govindapillai
> Sent: Thursday, August 22, 2024 5:50 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Govindapillai, Vinod <vinod.govindapillai@xxxxxxxxx>; Nikula, Jani
> <jani.nikula@xxxxxxxxx>; Saarinen, Jani <jani.saarinen@xxxxxxxxx>
> Subject: [PATCH v2] drm/i915: Implement Dbuf overlap detection feature starting
> from LNL
>
> From: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
>
> From LNL onwards there is a new hardware feature, which allows to detect if the
> driver wrongly allocated DBuf entries and they happen to overlap. If enabled this
> will cause a specific interrupt to occur.
> We now handle it in the driver, by writing correspondent error message to kernel
> log.
>
> v2: Initialize dbuf overlap flag in runtime_defaults (Jani Nikula)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++
> drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++
> drivers/gpu/drm/i915/display/intel_display_irq.c | 7 +++++++
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 4 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index b28d55fa0c3a..bd00db7d7b23 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -1089,6 +1089,7 @@ static const struct intel_display_device_info
> xe2_lpd_display = {
> .__runtime_defaults.fbc_mask =
> BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
> BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
> + .__runtime_defaults.has_dbuf_overlap_detection = true,
> };
>
> static const struct intel_display_device_info xe2_hpd_display = { @@ -1457,6
> +1458,10 @@ static void __intel_display_device_info_runtime_init(struct
> drm_i915_private *i9
> if (IS_DISPLAY_VER(i915, 10, 12) &&
> (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
> display_runtime->has_dsc = 0;
> +
> + if (DISPLAY_VER(i915) >= 20 &&
> + (dfsm & XE2LPD_DFSM_DBUF_OVERLAP_DISABLE))
> + display_runtime->has_dbuf_overlap_detection = false;
> }
>
> if (DISPLAY_VER(i915) >= 20) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> b/drivers/gpu/drm/i915/display/intel_display_device.h
> index ad60c676c84d..cb3b0006dfef 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -122,6 +122,7 @@ enum intel_display_subplatform {
> #define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)-
> >has_cdclk_squash)
> #define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) &&
> IS_DISPLAY_VER(i915, 7, 13))
> #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) ||
> IS_ALDERLAKE_S(i915))
> +#define HAS_DBUF_OVERLAP_DETECTION(__i915)
> +(DISPLAY_RUNTIME_INFO(__i915)->has_dbuf_overlap_detection)
> #define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi)
> #define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)-
> >pipe_mask != 0)
> #define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)-
> >has_dmc)
> @@ -218,6 +219,7 @@ struct intel_display_runtime_info {
> bool has_hdcp;
> bool has_dmc;
> bool has_dsc;
> + bool has_dbuf_overlap_detection;
> };
>
> struct intel_display_device_info {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index afcd2af82942..6bb78fb6c62c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -904,6 +904,13 @@ gen8_de_misc_irq_handler(struct drm_i915_private
> *dev_priv, u32 iir)
> struct intel_display *display = &dev_priv->display;
> bool found = false;
>
> + if (HAS_DBUF_OVERLAP_DETECTION(dev_priv)) {
> + if (iir & XE2LPD_DBUF_OVERLAP_DETECTED) {
Is this interrupt enabled by default ? if not we will need to unmask and enable
the interrupt as well.
> + drm_warn(&dev_priv->drm, "DBuf overlap
> detected\n");
> + found = true;
> + }
> + }
> +
> if (DISPLAY_VER(dev_priv) >= 14) {
> if (iir & (XELPDP_PMDEMAND_RSP |
> XELPDP_PMDEMAND_RSPTOUT_ERR)) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 569b461022c5..45a2989746a4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2580,6 +2580,7 @@
> #define GEN8_DE_MISC_GSE REG_BIT(27)
> #define GEN8_DE_EDP_PSR REG_BIT(19)
> #define XELPDP_PMDEMAND_RSP REG_BIT(3)
> +#define XE2LPD_DBUF_OVERLAP_DETECTED REG_BIT(1)
>
> #define GEN8_PCU_ISR _MMIO(0x444e0)
> #define GEN8_PCU_IMR _MMIO(0x444e4)
> @@ -2865,6 +2866,7 @@
> #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> #define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
> #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
> +#define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3)
>
> #define XE2LPD_DE_CAP _MMIO(0x41100)
> #define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
> --
> 2.34.1
