On Tue, 08 Oct 2024, Matt Atwood <matthew.s.atwood@xxxxxxxxx> wrote: > From: Suraj Kandpal <suraj.kandpal@xxxxxxxxx> > > Add new bit range for Max PHY Swing Setup in PORT_ALPM_CTL > register for DISPLAY_VER >= 30. > > Bspec: 70277 > Signed-off-by: Suraj Kandpal <suraj.kandpal@xxxxxxxxx> > Signed-off-by: Matt Atwood <matthew.s.atwood@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_alpm.c | 2 +- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 +++- > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c > index 55f3ae1e68c9..100ce776a203 100644 > --- a/drivers/gpu/drm/i915/display/intel_alpm.c > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c > @@ -334,7 +334,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, > intel_de_write(display, > PORT_ALPM_CTL(port), > PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | > - PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | > + PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(display, 15) | > PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | > PORT_ALPM_CTL_SILENCE_PERIOD( > intel_dp->alpm_parameters.silence_period_sym_clocks)); > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h > index 0841242543ca..046e400704e8 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > @@ -299,7 +299,9 @@ > #define PORT_ALPM_CTL(port) _MMIO_PORT(port, _PORT_ALPM_CTL_A, _PORT_ALPM_CTL_B) > #define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31) > #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20) > -#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val) > +#define PTL_PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(25, 20) > +#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(display, val) (DISPLAY_VER(display) >= 30 ? REG_FIELD_PREP(PTL_PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val) :\ > + REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val)) I'm inclined to think this is not a good direction. Please define separate macros for different platforms. BR, Jani. > #define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK REG_GENMASK(19, 16) > #define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, val) > #define PORT_ALPM_CTL_SILENCE_PERIOD_MASK REG_GENMASK(7, 0) -- Jani Nikula, Intel
