Re: [PATCH 5/7] drm/i915: Enable fp16 + CCS on TGL+

[Juha-Pekka Heikkila <juhapekka.heikkila@xxxxxxxxx>]

Here the same question on depth as on those two other patches, I think 
that field should have value other than zero. Otherwise all did look ok.

On 18.9.2024 17.44, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> TGL+ support compressed fp16 scanout. Enable it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
>   drivers/gpu/drm/i915/display/intel_fb.c       | 36 +++++++++++++++++++
>   .../drm/i915/display/skl_universal_plane.c    |  8 ++---
>   2 files changed, 40 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index 83495e165da7..2d384092416e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -87,6 +87,18 @@ static const struct drm_format_info gen12_ccs_formats[] = {
>   	{ .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
>   	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
>   	  .hsub = 1, .vsub = 1, .has_alpha = true },
> +	{ .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 2,
> +	  .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 },
> +	  .hsub = 1, .vsub = 1, },
> +	{ .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 2,
> +	  .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 },
> +	  .hsub = 1, .vsub = 1, },
> +	{ .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 2,
> +	  .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 },
> +	  .hsub = 1, .vsub = 1, .has_alpha = true },
> +	{ .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 2,
> +	  .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 },
> +	  .hsub = 1, .vsub = 1, .has_alpha = true },
>   	{ .format = DRM_FORMAT_YUYV, .num_planes = 2,
>   	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
>   	  .hsub = 2, .vsub = 1, .is_yuv = true },
> @@ -145,6 +157,18 @@ static const struct drm_format_info gen12_ccs_cc_formats[] = {
>   	{ .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
>   	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 },
>   	  .hsub = 1, .vsub = 1, .has_alpha = true },
> +	{ .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 3,
> +	  .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 },
> +	  .hsub = 1, .vsub = 1, },
> +	{ .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 3,
> +	  .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 },
> +	  .hsub = 1, .vsub = 1, },
> +	{ .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 3,
> +	  .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 },
> +	  .hsub = 1, .vsub = 1, .has_alpha = true },
> +	{ .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 3,
> +	  .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 },
> +	  .hsub = 1, .vsub = 1, .has_alpha = true },
>   };
>   
>   static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
> @@ -172,6 +196,18 @@ static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
>   	{ .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
>   	  .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
>   	  .hsub = 1, .vsub = 1, .has_alpha = true },
> +	{ .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 2,
> +	  .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
> +	  .hsub = 1, .vsub = 1, },
> +	{ .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 2,
> +	  .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
> +	  .hsub = 1, .vsub = 1, },
> +	{ .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 2,
> +	  .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
> +	  .hsub = 1, .vsub = 1, .has_alpha = true },
> +	{ .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 2,
> +	  .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 },
> +	  .hsub = 1, .vsub = 1, .has_alpha = true },
>   };
>   
>   struct intel_modifier_desc {
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 8817758ef10d..afaa92a6d91c 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2373,6 +2373,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>   	case DRM_FORMAT_XBGR2101010:
>   	case DRM_FORMAT_ARGB2101010:
>   	case DRM_FORMAT_ABGR2101010:
> +	case DRM_FORMAT_XBGR16161616F:
> +	case DRM_FORMAT_ABGR16161616F:
> +	case DRM_FORMAT_XRGB16161616F:
> +	case DRM_FORMAT_ARGB16161616F:
>   		if (intel_fb_is_ccs_modifier(modifier))
>   			return true;
>   		fallthrough;
> @@ -2391,10 +2395,6 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>   	case DRM_FORMAT_RGB565:
>   	case DRM_FORMAT_XVYU2101010:
>   	case DRM_FORMAT_C8:
> -	case DRM_FORMAT_XBGR16161616F:
> -	case DRM_FORMAT_ABGR16161616F:
> -	case DRM_FORMAT_XRGB16161616F:
> -	case DRM_FORMAT_ARGB16161616F:
>   	case DRM_FORMAT_Y210:
>   	case DRM_FORMAT_Y212:
>   	case DRM_FORMAT_Y216: