On Sat, Nov 02, 2013 at 09:07:49PM -0700, Ben Widawsky wrote:
> The current formula we use for HSW is not what is in current docs.
> However, changing to the HSW formula on my HSW does not improve power
> usage, and decreases performance by about 5% in limited xonotic testing.
>
> For gen8, until we know otherwise, or run experiments, let's use
> the HSW formula - which should be the same used in the Windows driver
> (and thus help make an apples-applies comparison) on gen8.
>
> Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6d14182..3dd30f7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3924,7 +3924,10 @@ void gen6_update_ring_freq(struct drm_device *dev)
> int diff = dev_priv->rps.max_delay - gpu_freq;
> unsigned int ia_freq = 0, ring_freq = 0;
>
> - if (IS_HASWELL(dev)) {
> + if (INTEL_INFO(dev)->gen > 7) {
Our coding style is to use >= 8 or < 8 to be consistent with 0 based C
arrays and so hopefully avoiding off-by-ones. I.e. I've spent a bit of
time being stumped until I've noticed that this is gen8+ and actually
doesn't apply to ivb. Fixed while applying.
-Daniel
> + /* max(2 * GT, DDR). NB: GT is 50MHz units */
> + ring_freq = max(min_ring_freq, gpu_freq);
> + } else if (IS_HASWELL(dev)) {
> ring_freq = mult_frac(gpu_freq, 5, 4);
> ring_freq = max(min_ring_freq, ring_freq);
> /* leave ia_freq as the default, chosen by cpufreq */
> --
> 1.8.4.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
