> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Arun
> R Murthy
> Sent: Thursday, September 19, 2024 7:02 PM
> To: intel-xe@xxxxxxxxxxxxxxxxxxxxx; intel-gfx@xxxxxxxxxxxxxxxxxxxxx; dri-
> devel@xxxxxxxxxxxxxxxxxxxxx
> Cc: Murthy, Arun R <arun.r.murthy@xxxxxxxxx>
> Subject: [PATCHv3 5/6] drm/i915/histogram: histogram delay counter doesnt
> reset
>
> The delay counter for histogram does not reset and as a result the
> histogram bin never gets updated. Workaround would be to use save and
> restore histogram register.
> HSD: 14014889975
Should be Wa: 14014889975
Regards,
Suraj Kandpal
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_histogram.c | 17 +++++++++++++++++
> .../gpu/drm/i915/display/intel_histogram_reg.h | 1 +
> 2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c
> b/drivers/gpu/drm/i915/display/intel_histogram.c
> index d1af64f2a6ac..6529a59ca6b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_histogram.c
> +++ b/drivers/gpu/drm/i915/display/intel_histogram.c
> @@ -74,6 +74,11 @@ static void intel_histogram_handle_int_work(struct
> work_struct *work)
> struct intel_display *display = to_intel_display(intel_crtc);
> char *histogram_event[] = {"HISTOGRAM=1", NULL};
>
> + /* Wa: 14014889975 */
> + if (IS_DISPLAY_VER(display, 12, 13))
> + intel_de_rmw(display, DPST_CTL(intel_crtc->pipe),
> + DPST_CTL_RESTORE, 0);
> +
> /*
> * TODO: PSR to be exited while reading the Histogram data
> * Set DPST_CTL Bin Reg function select to TC @@ -94,6 +99,12 @@
> static void intel_histogram_handle_int_work(struct work_struct *work)
> "sending HISTOGRAM event failed\n");
> }
>
> + /* Wa: 14014889975 */
> + if (IS_DISPLAY_VER(display, 12, 13))
> + /* Write the value read from DPST_CTL to
> DPST_CTL.Interrupt Delay Counter(bit 23:16) */
> + intel_de_write(display, DPST_CTL(intel_crtc->pipe),
> intel_de_read(display,
> + DPST_CTL(intel_crtc->pipe)) |
> DPST_CTL_RESTORE);
> +
> /* Enable histogram interrupt */
> intel_de_rmw(display, DPST_GUARD(intel_crtc->pipe),
> DPST_GUARD_HIST_INT_EN,
> DPST_GUARD_HIST_INT_EN);
> @@ -245,6 +256,12 @@ int intel_histogram_set_iet_lut(struct intel_crtc
> *intel_crtc, u32 *data)
> return -EINVAL;
> }
>
> + /* Wa: 14014889975 */
> + if (IS_DISPLAY_VER(display, 12, 13))
> + /* Write the value read from DPST_CTL to
> DPST_CTL.Interrupt Delay Counter(bit 23:16) */
> + intel_de_write(display, DPST_CTL(intel_crtc->pipe),
> intel_de_read(display,
> + DPST_CTL(intel_crtc->pipe)) |
> DPST_CTL_RESTORE);
> +
> /*
> * Set DPST_CTL Bin Reg function select to IE
> * Set DPST_CTL Bin Register Index to 0 diff --git
> a/drivers/gpu/drm/i915/display/intel_histogram_reg.h
> b/drivers/gpu/drm/i915/display/intel_histogram_reg.h
> index ed8f22aa8e75..ac392ed47463 100644
> --- a/drivers/gpu/drm/i915/display/intel_histogram_reg.h
> +++ b/drivers/gpu/drm/i915/display/intel_histogram_reg.h
> @@ -16,6 +16,7 @@
> #define DPST_CTL_RESTORE REG_BIT(28)
> #define DPST_CTL_IE_MODI_TABLE_EN REG_BIT(27)
> #define DPST_CTL_HIST_MODE REG_BIT(24)
> +#define DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT
> REG_GENMASK(23, 16)
> #define DPST_CTL_ENHANCEMENT_MODE_MASK
> REG_GENMASK(14, 13)
> #define DPST_CTL_EN_MULTIPLICATIVE
> REG_FIELD_PREP(DPST_CTL_ENHANCEMENT_MODE_MASK, 2)
> #define DPST_CTL_IE_TABLE_VALUE_FORMAT REG_BIT(15)
> --
> 2.25.1
