> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Jouni
> Högander
> Sent: Monday, 23 September 2024 7.32
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Hogander, Jouni <jouni.hogander@xxxxxxxxx>
> Subject: [PATCH 1/2] drm/i915/psr: Add new SU area calculation helper to apply
> workarounds
>
> intel_psr2_sel_fetch_update is already quite long function. Now we are about to
> add one more HW workaround. Let's split applying workarounds to selective
> update area into a separate function.
>
Reviewed-by: Mika Kahola <mika.kahola@xxxxxxxxx>
> Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 22 +++++++++++++++-------
> 1 file changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5b355d0a35652..f7dfd9435b589 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2488,11 +2488,24 @@ static bool
> psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
> return true;
> }
>
> +static void
> +intel_psr_apply_su_area_workarounds(struct intel_crtc_state
> +*crtc_state) {
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +
> + /* Wa_14014971492 */
> + if (!crtc_state->has_panel_replay &&
> + ((IS_DISPLAY_VER_STEP(display, IP_VER(14, 0), STEP_A0, STEP_B0) ||
> + IS_ALDERLAKE_P(i915) || IS_TIGERLAKE(i915))) &&
> + crtc_state->splitter.enable)
> + crtc_state->psr2_su_area.y1 = 0;
> +}
> +
> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct intel_display *display = to_intel_display(state);
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_plane_state *new_plane_state, *old_plane_state;
> struct intel_plane *plane;
> @@ -2597,12 +2610,7 @@ int intel_psr2_sel_fetch_update(struct
> intel_atomic_state *state,
> if (full_update)
> goto skip_sel_fetch_set_loop;
>
> - /* Wa_14014971492 */
> - if (!crtc_state->has_panel_replay &&
> - ((IS_DISPLAY_VER_STEP(display, IP_VER(14, 0), STEP_A0, STEP_B0) ||
> - IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv))) &&
> - crtc_state->splitter.enable)
> - crtc_state->psr2_su_area.y1 = 0;
> + intel_psr_apply_su_area_workarounds(crtc_state);
>
> ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
> if (ret)
> --
> 2.34.1
