> > -----Original Message-----
> > From: Intel-xe <intel-xe-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of
> > Arun R Murthy
> > Sent: Thursday, September 12, 2024 10:36 AM
> > To: intel-xe@xxxxxxxxxxxxxxxxxxxxx; intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > Cc: Murthy, Arun R <arun.r.murthy@xxxxxxxxx>; Srikanth V, NagaVenkata
> > <nagavenkata.srikanth.v@xxxxxxxxx>
> > Subject: [PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx for
> > timeout
> >
> > As per DP spec the timeout for LANE_CHANNEL_EQ_DONE is 400ms. But this
>
> Adding where in DP spec example dp2.1 section x.x is a good idea
>
Please refer to section 3.5.2.16.1 128b/132b DP LANEx_CHANNEL_EQ_DONE Sequnce
and Figure3-51: 128b/132b DP EQ Time Budget Illustration of DP2.1a spec.
> > timeout value is exclusively for the Aux RD Interval and excludes the
> > time consumed for the AUX Tx (i.e reading/writing FFE presets). Add
> > another 50ms for these AUX Tx to the 400ms timeout.
>
> Is this something we came up with by trial and error or is this also a part of spec
>
It's not by trail and erros. Timeout value of 450ms is part of DP.
> Regards,
> Suraj Kandpal
> >
> > Signed-off-by: Srikanth V NagaVenkata
> > <nagavenkata.srikanth.v@xxxxxxxxx>
> > Signed-off-by: Arun R Murthy <arun.r.murthy@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index ca179bed46ad..b6573934c6dd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -1414,7 +1414,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp
> > *intel_dp,
> > }
> >
> > /* Time budget for the LANEx_EQ_DONE Sequence */
> > - deadline = jiffies + msecs_to_jiffies_timeout(400);
> > + deadline = jiffies + msecs_to_jiffies_timeout(450);
> >
> > for (try = 0; try < max_tries; try++) {
> > fsleep(delay_us);
> > --
> > 2.25.1
