Quoting Ville Syrjala (2024-09-11 12:18:36-03:00)
>From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
>According to the eDP spec, the source must first configure all
>PSR related DPCD registers apart from the actual enable bit,
>and only then set the enable bit. Split the current single DPCD
>write to two to match the spec.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Gustavo Sousa <gustavo.sousa@xxxxxxxxx>
>---
> drivers/gpu/drm/i915/display/intel_psr.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>index 1a4ef231a53c..2b7c0c73f335 100644
>--- a/drivers/gpu/drm/i915/display/intel_psr.c
>+++ b/drivers/gpu/drm/i915/display/intel_psr.c
>@@ -745,7 +745,7 @@ static void _psr_enable_sink(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(intel_dp);
>- u8 val = DP_PSR_ENABLE;
>+ u8 val = 0;
>
> if (crtc_state->has_sel_update) {
> val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
>@@ -765,7 +765,9 @@ static void _psr_enable_sink(struct intel_dp *intel_dp,
>
> if (intel_dp->psr.entry_setup_frames > 0)
> val |= DP_PSR_FRAME_CAPTURE;
>+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);
>
>+ val |= DP_PSR_ENABLE;
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);
> }
>
>--
>2.44.2
>
