On Tue, 10 Sep 2024, "Pottumuttu, Sai Teja" <sai.teja.pottumuttu@xxxxxxxxx> wrote: > On 10-09-2024 11:53, Dnyaneshwar Bhadane wrote: >> Add new PCI id for ARL platform. >> >> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@xxxxxxxxx> > > I assume that you would send another patch to sync this PCI ID addition > in xe_pciids.h as well Yes, preferrably send both at the same time, even though one is to be merged to drm-intel-next and the other to drm-xe-next. We don't want the PCI IDs to be out of sync. Lucas, Rodrigo, another reason for [1]. BR, Jani. [1] https://lore.kernel.org/r/5e703ab69846d519335f3e7f5bcf84ff1704cd09.1725297097.git.jani.nikula@xxxxxxxxx > > With that, > > Reviewed-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@xxxxxxxxx> > >> --- >> include/drm/intel/i915_pciids.h | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/include/drm/intel/i915_pciids.h b/include/drm/intel/i915_pciids.h >> index cbb12fdbcb7f..02156c6f79b6 100644 >> --- a/include/drm/intel/i915_pciids.h >> +++ b/include/drm/intel/i915_pciids.h >> @@ -769,7 +769,8 @@ >> MACRO__(0x7D41, ## __VA_ARGS__), \ >> MACRO__(0x7D51, ## __VA_ARGS__), \ >> MACRO__(0x7D67, ## __VA_ARGS__), \ >> - MACRO__(0x7DD1, ## __VA_ARGS__) >> + MACRO__(0x7DD1, ## __VA_ARGS__), \ >> + MACRO__(0xB640, ## __VA_ARGS__) >> >> /* MTL */ >> #define INTEL_MTL_IDS(MACRO__, ...) \ -- Jani Nikula, Intel
