On 03.11.2013 18:13, Daniel Vetter wrote:
Have you tried my patch to reorder the dvo sequence a bit? That /should/
get all these things right:
http://www.spinics.net/lists/intel-gfx/msg34349.html
There's also a follow-up patch for you to test:
http://www.spinics.net/lists/intel-gfx/msg34350.html
That would prove that the first patch does indeed work. Note that patch 1
in this series is already merged.
Sorry, but using an external monitor is still not working correctly.
When booting with an external monitor connected, I either get no image
at all (bios = internal) or flickering on the external monitor and
nothing internally (bios = shared). When connecting the external monitor
after X has started, I can get a working image on the monitor, but not
on the internal panel. The DVO locks up again. If I configure the
internal panel, then reconfigure the VGA, I get a stable image. If I try
to change the internal panel dimensions then, I get a flickering
external screen. The DVO is locked up in either case.
I get the following when switching internally from 800x600 to 1024x768
(just as an example):
/* snip */
Nov 3 20:12:20 tyleet kernel: [ 1399.497881] [drm:drm_mode_setcrtc],
[CRTC:4]
Nov 3 20:12:20 tyleet kernel: [ 1399.497890]
[drm:drm_framebuffer_reference], FB ID: 39
Nov 3 20:12:20 tyleet kernel: [ 1399.497907] [drm:drm_mode_setcrtc],
[CONNECTOR:8:DVI-I-1]
Nov 3 20:12:20 tyleet kernel: [ 1399.497916]
[drm:intel_crtc_set_config], [CRTC:4] [FB:39] #connectors=1 (x y) (0 0)
Nov 3 20:12:20 tyleet kernel: [ 1399.497928]
[drm:intel_set_config_compute_mode_changes], modes are different, full
mode set
Nov 3 20:12:20 tyleet kernel: [ 1399.497935]
[drm:drm_mode_debug_printmodeline], Modeline 16:"" 0 40000 800 840 968
1056 600 601 605 628 0x0 0x5
Nov 3 20:12:20 tyleet kernel: [ 1399.497948]
[drm:drm_mode_debug_printmodeline], Modeline 16:"" 0 65000 1024 1048
1184 1344 768 771 777 806 0x0 0xa
Nov 3 20:12:20 tyleet kernel: [ 1399.497960]
[drm:intel_set_config_compute_mode_changes], computed changes for
[CRTC:4], mode_changed=1, fb_changed=0
Nov 3 20:12:20 tyleet kernel: [ 1399.497970]
[drm:intel_modeset_stage_output_state], [CONNECTOR:5:VGA-1] to [CRTC:3]
Nov 3 20:12:20 tyleet kernel: [ 1399.497978]
[drm:intel_modeset_stage_output_state], [CONNECTOR:8:DVI-I-1] to [CRTC:4]
Nov 3 20:12:20 tyleet kernel: [ 1399.497991]
[drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2,
prepare: 2, disable: 0
Nov 3 20:12:20 tyleet kernel: [ 1399.498008]
[drm:connected_sink_compute_bpp], [CONNECTOR:8:DVI-I-1] checking for
sink bpp constrains
Nov 3 20:12:20 tyleet kernel: [ 1399.498020]
[drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
Nov 3 20:12:20 tyleet kernel: [ 1399.498028]
[drm:intel_dump_pipe_config], [CRTC:4][modeset] config for pipe B
Nov 3 20:12:20 tyleet kernel: [ 1399.498036]
[drm:intel_dump_pipe_config], cpu_transcoder: B
Nov 3 20:12:20 tyleet kernel: [ 1399.498042]
[drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
Nov 3 20:12:20 tyleet kernel: [ 1399.498049]
[drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n:
0, link_m: 0, link_n: 0, tu: 0
Nov 3 20:12:20 tyleet kernel: [ 1399.498058]
[drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0,
link_n: 0, tu: 0
Nov 3 20:12:20 tyleet kernel: [ 1399.498066]
[drm:intel_dump_pipe_config], requested mode:
Nov 3 20:12:20 tyleet kernel: [ 1399.498072]
[drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 65000 1024 1048 1184
1344 768 771 777 806 0x0 0xa
Nov 3 20:12:20 tyleet kernel: [ 1399.498084]
[drm:intel_dump_pipe_config], adjusted mode:
Nov 3 20:12:20 tyleet kernel: [ 1399.498090]
[drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 65000 1024 1048 1184
1344 768 771 777 806 0x0 0xa
Nov 3 20:12:20 tyleet kernel: [ 1399.498102]
[drm:intel_dump_crtc_timings], crtc timings: 65000 1024 1048 1184 1344
768 771 777 806, type: 0x0 flags: 0xa
Nov 3 20:12:20 tyleet kernel: [ 1399.498112]
[drm:intel_dump_pipe_config], port clock: 65000
Nov 3 20:12:20 tyleet kernel: [ 1399.498118]
[drm:intel_dump_pipe_config], pipe src size: 1024x768
Nov 3 20:12:20 tyleet kernel: [ 1399.498125]
[drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios:
0x00000000, lvds border: 0x00000000
Nov 3 20:12:20 tyleet kernel: [ 1399.498132]
[drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size:
0x00000000, disabled
Nov 3 20:12:20 tyleet kernel: [ 1399.498140]
[drm:intel_dump_pipe_config], ips: 0
Nov 3 20:12:20 tyleet kernel: [ 1399.498145]
[drm:intel_dump_pipe_config], double wide: 0
Nov 3 20:12:20 tyleet kernel: [ 1399.498158] [drm:ns2501_dpms],
ns2501_dpms: Trying set the dpms of the DVO to 0
Nov 3 20:12:20 tyleet kernel: [ 1399.498438] [drm:ns2501_writeb],
Unable to write register 0x08 to i915 gmbus dpb:56
Nov 3 20:12:20 tyleet kernel: [ 1399.498703] [drm:ns2501_writeb],
Unable to write register 0x34 to i915 gmbus dpb:56
Nov 3 20:12:20 tyleet kernel: [ 1399.498968] [drm:ns2501_writeb],
Unable to write register 0x35 to i915 gmbus dpb:56
Nov 3 20:12:20 tyleet kernel: [ 1399.498976] [drm:enable_dvo],
enable_dvo: Trying to re-enable the DVO
Nov 3 20:12:20 tyleet kernel: [ 1399.498985] [drm:enable_dvo], DVOA
ctrl 0x00000000
Nov 3 20:12:20 tyleet kernel: [ 1399.498991] [drm:enable_dvo], DVOB
ctrl 0x80004084
Nov 3 20:12:20 tyleet kernel: [ 1399.499006] [drm:enable_dvo], DVOC
ctrl 0xd000409c
Nov 3 20:12:20 tyleet kernel: [ 1399.499013] [drm:enable_dvo], PLL A
ctrl 0x90a00000
Nov 3 20:12:20 tyleet kernel: [ 1399.499021] [drm:enable_dvo], PLL B
ctrl 0xd0840000
Nov 3 20:12:20 tyleet kernel: [ 1399.501050]
[drm:drm_calc_vbltimestamp_from_scanoutpos], crtc 1 : v 5 p(0,111)@
1399.501043 -> 1399.498113 [e 6 us, 0 rep]
Nov 3 20:12:20 tyleet kernel: [ 1399.521076] [drm:i830_get_fifo_size],
FIFO size - (0x00017e5f) A: 47
Nov 3 20:12:20 tyleet kernel: [ 1399.521103] [drm:intel_calculate_wm],
FIFO entries required for mode: 99
Nov 3 20:12:20 tyleet kernel: [ 1399.521110] [drm:intel_calculate_wm],
FIFO watermark level: -54
Nov 3 20:12:20 tyleet kernel: [ 1399.521116] [drm:i830_update_wm],
Setting FIFO watermarks - A: 1
Nov 3 20:12:20 tyleet kernel: [ 1399.521139] [drm:drm_vblank_get],
enabling vblank on crtc 1, ret: -22
Nov 3 20:12:20 tyleet kernel: [ 1399.529131] [drm:i8xx_update_pll],
computed PLL value is 0xd0820000
Nov 3 20:12:20 tyleet kernel: [ 1399.529139] [drm:i8xx_update_pll],
clock P1 is 4
Nov 3 20:12:20 tyleet kernel: [ 1399.529150] [drm:i8xx_update_pll],
clock P2 is 4
Nov 3 20:12:20 tyleet kernel: [ 1399.529279] [drm:i9xx_update_plane],
Writing base 02C00000 00000000 0 0 8192
Nov 3 20:12:20 tyleet kernel: [ 1399.529301] [drm:intel_crtc_mode_set],
[ENCODER:7:None-7] set [MODE:0:]
Nov 3 20:12:20 tyleet kernel: [ 1399.552060] [drm:ns2501_mode_set],
ns2501_mode_set: set mode
(hdisplay=1024,htotal=1344,vdisplay=768,vtotal=806).
Nov 3 20:12:20 tyleet kernel: [ 1399.552081] [drm:ns2501_mode_set],
ns2501_mode_set: switching to 1024x768
Nov 3 20:12:20 tyleet kernel: [ 1399.552375] [drm:ns2501_writeb],
Unable to write register 0x37 to i915 gmbus dpb:56
Nov 3 20:12:20 tyleet kernel: [ 1399.552641] [drm:ns2501_writeb],
Unable to write register 0x08 to i915 gmbus dpb:56
Nov 3 20:12:20 tyleet kernel: [ 1399.552650] [drm:enable_dvo],
enable_dvo: Trying to re-enable the DVO
Nov 3 20:12:20 tyleet kernel: [ 1399.552659] [drm:enable_dvo], DVOA
ctrl 0x00000000
Nov 3 20:12:20 tyleet kernel: [ 1399.552665] [drm:enable_dvo], DVOB
ctrl 0x80004084
Nov 3 20:12:20 tyleet kernel: [ 1399.552675] [drm:enable_dvo], DVOC
ctrl 0xd0004084
Nov 3 20:12:20 tyleet kernel: [ 1399.552682] [drm:enable_dvo], PLL A
ctrl 0x90a00000
Nov 3 20:12:20 tyleet kernel: [ 1399.552689] [drm:enable_dvo], PLL B
ctrl 0xd0820000
Nov 3 20:12:20 tyleet kernel: [ 1399.552697] [drm:ns2501_mode_set],
ns2501_mode_set: switching to 1024x768
Nov 3 20:12:20 tyleet kernel: [ 1399.554019] [drm:ns2501_dpms],
ns2501_dpms: Trying set the dpms of the DVO to 1
Nov 3 20:12:20 tyleet kernel: [ 1399.554282] [drm:ns2501_writeb],
Unable to write register 0x08 to i915 gmbus dpb:56
Nov 3 20:12:20 tyleet kernel: [ 1399.554546] [drm:ns2501_writeb],
Unable to write register 0x34 to i915 gmbus dpb:56
Nov 3 20:12:20 tyleet kernel: [ 1399.554810] [drm:ns2501_writeb],
Unable to write register 0x35 to i915 gmbus dpb:56
Nov 3 20:12:20 tyleet kernel: [ 1399.554817] [drm:enable_dvo],
enable_dvo: Trying to re-enable the DVO
Nov 3 20:12:20 tyleet kernel: [ 1399.554825] [drm:enable_dvo], DVOA
ctrl 0x00000000
Nov 3 20:12:20 tyleet kernel: [ 1399.554831] [drm:enable_dvo], DVOB
ctrl 0x80004084
Nov 3 20:12:20 tyleet kernel: [ 1399.554839] [drm:enable_dvo], DVOC
ctrl 0xd0004084
Nov 3 20:12:20 tyleet kernel: [ 1399.554846] [drm:enable_dvo], PLL A
ctrl 0x90a00000
Nov 3 20:12:20 tyleet kernel: [ 1399.554853] [drm:enable_dvo], PLL B
ctrl 0xd0820000
Nov 3 20:12:20 tyleet kernel: [ 1399.558625]
[drm:drm_calc_timestamping_constants], crtc 4: hwmode: htotal 1344,
vtotal 806, vdisplay 768
Nov 3 20:12:20 tyleet kernel: [ 1399.558646]
[drm:drm_calc_timestamping_constants], crtc 4: clock 65000 kHz framedur
16665600 linedur 20676, pixeldur 15
Nov 3 20:12:20 tyleet kernel: [ 1399.558673]
[drm:intel_connector_check_state], [CONNECTOR:5:VGA-1]
Nov 3 20:12:20 tyleet kernel: [ 1399.558943] [drm:ns2501_readb], Unable
to read register 0x08 from i915 gmbus dpb:0x38.
Nov 3 20:12:20 tyleet kernel: [ 1399.558955] [drm:check_encoder_state],
[ENCODER:6:DAC-6]
Nov 3 20:12:20 tyleet kernel: [ 1399.558964] [drm:check_encoder_state],
[ENCODER:7:None-7]
Nov 3 20:12:20 tyleet kernel: [ 1399.558972] [drm:check_crtc_state],
[CRTC:3]
Nov 3 20:12:20 tyleet kernel: [ 1399.559005] [drm:check_crtc_state],
[CRTC:4]
Nov 3 20:12:20 tyleet kernel: [ 1399.559027]
[drm:drm_framebuffer_reference], FB ID: 39
Nov 3 20:12:20 tyleet kernel: [ 1399.559036]
[drm:drm_framebuffer_unreference], FB ID: 39
Nov 3 20:12:20 tyleet kernel: [ 1399.559042]
[drm:drm_framebuffer_reference], FB ID: 39
Nov 3 20:12:20 tyleet kernel: [ 1399.559047]
[drm:drm_framebuffer_unreference], FB ID: 39
Nov 3 20:12:20 tyleet kernel: [ 1399.559059]
[drm:drm_framebuffer_unreference], FB ID: 39
/* snip */
The drm:enable_dvo lines are from my current version of the patch and
dump the corresponding i835 registers.
Note the following: Assuming that the internal panel is feed by pipe B
(I hope I assume right) then the PLL registers
are off. They should be 0xd0820000, but the PLL for pipe B is configured
to 0xd0840000.
I'll check later what this bit precisely means. One way or another, the
PLL configuration is not correct to feed the DVO,
and hence I'll get a frozen DVO again. )-:
Greetings,
Thomas
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