On Mon, 08 Jul 2024, Animesh Manna <animesh.manna@xxxxxxxxx> wrote:
> Panel Replay VSC SDP not getting sent when VRR is enabled
> and W1 and W2 are 0. So Program Set Context Latency in
> TRANS_SET_CONTEXT_LATENCY register to at least a value of 1.
> The same is applicable for PSR1/PSR2 as well.
>
> HSD: 14015406119
>
> v1: Initial version.
> v2: Update timings stored in adjusted_mode struct. [Ville]
> v3: Add WA in compute_config(). [Ville]
> v4:
> - Add DISPLAY_VER() check and improve code comment. [Rodrigo]
> - Introduce centralized intel_crtc_vblank_delay(). [Ville]
> v5: Move to crtc_compute_config(). [Ville]
> v6: Restrict DISPLAY_VER till 14. [Mitul]
> v7:
> - Corrected code-comment. [Mitul]
> - dev_priv local variable removed. [Jani]
> v8: Introduce late_compute_config() which will take care late
> vblank-delay adjustment. [Ville]
> v9: Implementation simplified and split into multiple patches.
>
> Signed-off-by: Animesh Manna <animesh.manna@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 50 +++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_display.h | 2 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 13 -----
> 3 files changed, 51 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c2c388212e2e..be30eb22f3d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2512,9 +2512,21 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
> static int intel_crtc_compute_config(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> + struct drm_connector *connector;
> + struct drm_connector_state *connector_state;
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - int ret;
> + int ret, i;
> +
> + for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
for_each_new_intel_connector_in_state()
> + struct intel_encoder *encoder =
> + to_intel_encoder(connector_state->best_encoder);
> +
> + if (connector_state->crtc != &crtc->base)
> + continue;
> +
> + intel_crtc_adjust_vblank_delay(crtc_state, encoder);
> + }
>
> ret = intel_dpll_crtc_compute_clock(state, crtc);
> if (ret)
> @@ -3925,6 +3937,26 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
> return true;
> }
>
> +void intel_crtc_adjust_vblank_delay(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +
> + /*
> + * wa_14015401596 for display versions 13, 14.
> + * Program Set Context Latency in TRANS_SET_CONTEXT_LATENCY register
> + * to at least a value of 1 when PSR1/PSR2/Panel Replay is enabled with VRR.
> + * Value for TRANS_SET_CONTEXT_LATENCY is calculated by substracting
> + * crtc_vdisplay from crtc_vblank_start, so incrementing crtc_vblank_start
> + * by 1 if both are equal.
> + */
> + if (crtc_state->vrr.enable && crtc_state->has_psr &&
> + adjusted_mode->crtc_vblank_start == adjusted_mode->crtc_vdisplay &&
> + IS_DISPLAY_VER(to_i915(crtc->base.dev), 13, 14))
> + adjusted_mode->crtc_vblank_start += 1;
> +}
> +
> int intel_dotclock_calculate(int link_freq,
> const struct intel_link_m_n *m_n)
> {
> @@ -4783,10 +4815,26 @@ intel_modeset_pipe_config_late(struct intel_atomic_state *state,
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> struct drm_connector_state *conn_state;
> struct drm_connector *connector;
> int i;
>
> + if (crtc_state->vrr.enable) {
> + /*
> + * For XE_LPD+, we use guardband and pipeline override
> + * is deprecated.
> + */
> + if (DISPLAY_VER(to_i915(crtc->base.dev)) >= 13) {
> + crtc_state->vrr.guardband =
> + crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start;
> + } else {
> + crtc_state->vrr.pipeline_full =
> + min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
> + crtc_state->framestart_delay - 1);
> + }
> + }
> +
> for_each_new_connector_in_state(&state->base, connector,
> conn_state, i) {
> struct intel_encoder *encoder =
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index b0cf6ca70952..21fd330b8834 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -428,6 +428,8 @@ bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);
> u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);
> struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state);
> bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
> +void intel_crtc_adjust_vblank_delay(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder);
> bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> const struct intel_crtc_state *pipe_config,
> bool fastset);
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 5a0da64c7db3..46341367d250 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -242,19 +242,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> (crtc_state->hw.adjusted_mode.crtc_vtotal -
> crtc_state->hw.adjusted_mode.vsync_end);
> }
> -
> - /*
> - * For XE_LPD+, we use guardband and pipeline override
> - * is deprecated.
> - */
> - if (DISPLAY_VER(i915) >= 13) {
> - crtc_state->vrr.guardband =
> - crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start;
> - } else {
> - crtc_state->vrr.pipeline_full =
> - min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
> - crtc_state->framestart_delay - 1);
> - }
> }
>
> static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
--
Jani Nikula, Intel
