MSA Ignore Timing PAR enable is set in the DP sink when we enable variable
refresh rate. When using VRR timing generator for fixed refresh rate
we do not want to ignore the mode timings, as the refresh rate is still
fixed. Modify the checks to enable MSA Ignore Timing PAR only when not
in fixed_rr mode.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 8 +++++++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 25ff3ff0ab95..f6df1de2c6a3 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2213,7 +2213,7 @@ static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- if (!crtc_state->vrr.enable)
+ if (!crtc_state->vrr.enable || crtc_state->vrr.fixed_rr)
return;
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 9c8738295106..4820a4bdbe26 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -718,8 +718,14 @@ void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, b
static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
+ bool enable_msa_timing_par_ignore;
+
+ /* Enable MSA TIMING PAR IGNORE only in non fixed_rr mode */
+ if (crtc_state->vrr.enable && !crtc_state->vrr.fixed_rr)
+ enable_msa_timing_par_ignore = true;
+
intel_dp_link_training_set_mode(intel_dp,
- crtc_state->port_clock, crtc_state->vrr.flipline);
+ crtc_state->port_clock, enable_msa_timing_par_ignore);
}
void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
--
2.45.2
