On Wed, Aug 28, 2024 at 10:20:15AM +0200, Andi Shyti wrote: > Hi Sima, > > first of all, thanks for looking into this series. > > On Tue, Aug 27, 2024 at 07:31:21PM +0200, Daniel Vetter wrote: > > On Fri, Aug 23, 2024 at 03:08:40PM +0200, Andi Shyti wrote: > > > Hi, > > > > > > This patch series introduces static load balancing for GPUs with > > > multiple compute engines. It's a lengthy series, and some > > > challenging aspects still need to be resolved. > > > > Do we have an actual user for this, where just reloading the entire driver > > (or well-rebinding, if you only want to change the value for a specific > > device) with a new module option isn't enough? > > Yes, we have users for this and this has been already agreed with > architects and maintainers. So my understanding is that for upstream, this only applies to dg2, because the other platforms don't have enough CCS engines to make this a real issue. Do we really have upstream demand for this feature on dg2 only? Also how hard would it be to make these users happy with xe-on-dg2 in upstream instead? > Why are you saying that we are reloading/rebinding the driver? That's the other alternate solution. > I'm only removing the exposure of user engines, which is > basically a flag in the engines data structure. > > > There's some really gnarly locking and lifetime fun in there, and it needs > > a corresponding justification. > > What locking are you referring about? > > I only added one single mutex that has a comment and a > justification. If you think that's not enough, I can of course > improve it (please note that the changes have a good amount of > comments and I tried to be aso more descriptive as I could). > > When I change the engines configurations only for the compute > engines and only for DG2 platforms, I need to make sure that no > other user is affected by the change. Thus I need to make sure > that access to some of the strucures are properly serialized. > > > Which needs to be enormous for this case, > > meaning actual customers willing to shout on dri-devel that they really, > > absolutely need this, or their machines will go up in flames. > > Otherwise this is a nack from me. > > Would you please tell me why are you nacking the patch? So that I > address your comments for v4? So for one, this is substantially more flexible than the solution merged into xe. And the patch set doesn't explain why (the commit messages actualy describe the design xe has). That does not inspire confidence at all. Second, I don't think anyone understands the entire engine/ctx locking design in i915-gem. And the fix for that was to make as much as absolutely possible immutable. Yes the implementation looks correct, but when I looked at the much, much simpler xe implementation I'm pretty sure I've found an issue there too. Here I can't even tell. -Sima -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
