+Cc Nanley from the Mesa team since he implemented the Wa_1808121037 code and will probably know best if/how the Mesa code should be updated to also address the DG2 + MTL performance tuning setting recommended on bspec 68331. Matt > } > > static void > @@ -1570,6 +1577,12 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > /* Wa_14015795083 */ > wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); > } > + /* > + * DisableHIZPlaneOptimizationForRedundantZPlaneUnit > + * This is not WA, This is required by recommended tuning setting. > + */ > + wa_masked_dis(wal, > + GEN7_COMMON_SLICE_CHICKEN1, HIZ_PLANE_OPTIMIZATION_DISABLE); > > /* > * Unlike older platforms, we no longer setup implicit steering here; > @@ -2072,7 +2085,7 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine) > case RENDER_CLASS: > /* Required by recommended tuning setting (not a workaround) */ > whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); > - > + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); > break; > default: > break; > @@ -2087,7 +2100,7 @@ static void xelpg_whitelist_build(struct intel_engine_cs *engine) > case RENDER_CLASS: > /* Required by recommended tuning setting (not a workaround) */ > whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); > - > + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); > break; > default: > break; > -- > 2.34.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
