> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Suraj
> Kandpal
> Sent: Thursday, May 9, 2024 8:59 AM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@xxxxxxxxx>;
> Kandpal, Suraj <suraj.kandpal@xxxxxxxxx>
> Subject: [PATCH] drm/i915/pps: Disable DPLS_GATING around pps sequence
>
> Disable bit 29 of SCLKGATE_DIS register around pps sequence when we turn
> panel power on.
>
> --v2
> -Squash two commit together [Jani]
> -Use IS_DISPLAY_VER [Jani]
> -Fix multiline comment [Jani]
>
> --v3
> -Define register in a more appropriate place [Mitul]
>
> Bspec: 49304
> Signed-off-by: Suraj Kandpal <suraj.kandpal@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_pps.c | 12 ++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> b/drivers/gpu/drm/i915/display/intel_pps.c
> index 0ccbf9a85914..d774aeb1673e 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -948,6 +948,14 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
> intel_de_posting_read(dev_priv, pp_ctrl_reg);
> }
>
> + /*
Hi Suraj,
> + * WA: 16023567976
--------------------^^^^^^^^ is not the correct WA number.
Please mention the linage number here.
> + * Disable DPLS gating around power sequence.
> + */
> + if (IS_DISPLAY_VER(dev_priv, 12, 14))
Also, I did not find the link to the display version 12 for this WA.
I could see the target display version for this WA is 13.00 and 14.00 as a permanent WA for now.
Dnyaneshwar
> + intel_de_rmw(dev_priv, SCLKGATE_DIS,
> + 0, DPLS_GATING_DISABLE);
> +
> pp |= PANEL_POWER_ON;
> if (!IS_IRONLAKE(dev_priv))
> pp |= PANEL_POWER_RESET;
> @@ -958,6 +966,10 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
> wait_panel_on(intel_dp);
> intel_dp->pps.last_power_on = jiffies;
>
> + if (IS_DISPLAY_VER(dev_priv, 12, 14))
> + intel_de_rmw(dev_priv, SCLKGATE_DIS,
> + DPLS_GATING_DISABLE, 0);
> +
> if (IS_IRONLAKE(dev_priv)) {
> pp |= PANEL_POWER_RESET; /* restore panel reset bit */
> intel_de_write(dev_priv, pp_ctrl_reg, pp); diff --git
> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
> 5670eee4a498..4cc82360298b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5151,6 +5151,10 @@ enum skl_power_gate {
>
> #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
>
> +/* SCLKGATE_DIS */
> +#define SCLKGATE_DIS _MMIO(0xc2020)
> +#define DPLS_GATING_DISABLE REG_BIT(29)
> +
> /* Plane CSC Registers */
> #define _PLANE_CSC_RY_GY_1_A 0x70210
> #define _PLANE_CSC_RY_GY_2_A 0x70310
> --
> 2.43.2
