Check SPI access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Signed-off-by: Alexander Usyskin <alexander.usyskin@xxxxxxxxx>
---
drivers/gpu/drm/i915/spi/intel_spi.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c b/drivers/gpu/drm/i915/spi/intel_spi.c
index 200139531d26..e2b76e5cbc0c 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi.c
+++ b/drivers/gpu/drm/i915/spi/intel_spi.c
@@ -10,6 +10,7 @@
#include "spi/intel_spi.h"
#define GEN12_GUNIT_SPI_SIZE 0x80
+#define HECI_FW_STATUS_2_SPI_ACCESS_MODE BIT(3)
static const struct intel_dg_spi_region regions[INTEL_DG_SPI_REGIONS] = {
[0] = { .name = "DESCRIPTOR", },
@@ -22,6 +23,29 @@ static void i915_spi_release_dev(struct device *dev)
{
}
+static bool i915_spi_writeable_override(struct drm_i915_private *dev_priv)
+{
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ resource_size_t base;
+ bool writeable_override;
+
+ if (IS_DG1(dev_priv)) {
+ base = DG1_GSC_HECI2_BASE;
+ } else if (IS_DG2(dev_priv)) {
+ base = DG2_GSC_HECI2_BASE;
+ } else {
+ dev_err(&pdev->dev, "Unknown platform\n");
+ return true;
+ }
+
+ writeable_override =
+ !(intel_uncore_read(&dev_priv->uncore, HECI_FWSTS(base, 2)) &
+ HECI_FW_STATUS_2_SPI_ACCESS_MODE);
+ if (writeable_override)
+ dev_info(&pdev->dev, "SPI access overridden by jumper\n");
+ return writeable_override;
+}
+
void intel_spi_init(struct drm_i915_private *dev_priv)
{
struct intel_dg_spi_dev *spi = &dev_priv->spi;
@@ -33,6 +57,7 @@ void intel_spi_init(struct drm_i915_private *dev_priv)
if (!IS_DGFX(dev_priv))
return;
+ spi->writeable_override = i915_spi_writeable_override(dev_priv);
spi->bar.parent = &pdev->resource[0];
spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start;
spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;
--
2.34.1
