[RFC PATCH 8/9] drm/i915/gt: Allow the user to change the CCS mode through sysfs

[Andi Shyti <andi.shyti@xxxxxxxxxxxxxxx>]

Create the 'ccs_mode' file under

/sys/class/drm/cardX/gt/gt0/ccs_mode

This file allows the user to read and set the current CCS mode.

 - Reading: The user can read the current CCS mode, which can be
   1, 2, or 4. This value is derived from the current engine
   mask.

 - Writing: The user can set the CCS mode to 1, 2, or 4,
   depending on the desired number of exposed engines and the
   required load balancing.

The interface will return -EBUSY if other clients are connected
to i915, or -EINVAL if an invalid value is set.

Signed-off-by: Andi Shyti <andi.shyti@xxxxxxxxxxxxxxx>
---
 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 108 ++++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
index 0d733b3e8df3..7773a04981a4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
@@ -4,10 +4,27 @@
  */
 
 #include "i915_drv.h"
+#include "intel_engine_user.h"
 #include "intel_gt_ccs_mode.h"
+#include "intel_gt_pm.h"
 #include "intel_gt_print.h"
 #include "intel_gt_regs.h"
 #include "intel_gt_sysfs.h"
+#include "i915_perf.h"
+#include "sysfs_engines.h"
+
+static void engine_update_mask(struct intel_gt *gt, u32 ccs_mode)
+{
+	unsigned long ccs_mask = gt->ccs.cslice_mask;
+	struct intel_gt_info *info = &gt->info;
+	int i;
+
+	/* Mask off all the CCS engines */
+	info->engine_mask &= ~GENMASK(CCS3, CCS0);
+
+	for_each_set_bit(i, &ccs_mask, I915_MAX_CCS)
+		info->engine_mask |= BIT(_CCS(i));
+}
 
 void intel_gt_ccs_mode_init(struct intel_gt *gt)
 {
@@ -148,6 +165,86 @@ static ssize_t num_cslices_show(struct device *dev,
 }
 static DEVICE_ATTR_RO(num_cslices);
 
+static ssize_t ccs_mode_show(struct device *dev,
+			     struct device_attribute *attr, char *buff)
+{
+	struct intel_gt *gt = kobj_to_gt(&dev->kobj);
+	u32 ccs_mode;
+
+	ccs_mode = hweight32(CCS_MASK(gt));
+
+	return sysfs_emit(buff, "%u\n", ccs_mode);
+}
+
+static ssize_t ccs_mode_store(struct device *dev,
+			      struct device_attribute *attr,
+			      const char *buff, size_t count)
+{
+	struct intel_gt *gt = kobj_to_gt(&dev->kobj);
+	int num_cslices = hweight32(gt->ccs.cslice_mask);
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	intel_wakeref_t wakeref;
+	ssize_t ret;
+	u32 val;
+
+	/*
+	 * We don't want to change the CCS
+	 * mode while someone is using the GT
+	 */
+	if (intel_gt_pm_is_awake(gt))
+		return -EBUSY;
+
+	ret = kstrtou32(buff, 0, &val);
+	if (ret)
+		return ret;
+
+	/*
+	 * As of now possible values to be set are 1, 2, 4,
+	 * up to the maximum number of available slices
+	 */
+	if ((!val) || (val > num_cslices) || (num_cslices % val))
+		return -EINVAL;
+
+	/*
+	 * Nothing to do if the requested setting
+	 * is the same as the current one
+	 */
+	if (val == hweight32(CCS_MASK(gt)))
+		return count;
+
+	/* Recreate engine exposure */
+	intel_engines_remove_sysfs(gt->i915);
+
+	mutex_lock(&gt->ccs.mutex);
+	intel_gt_apply_ccs_mode(gt, val - 1);
+	mutex_unlock(&gt->ccs.mutex);
+
+	wakeref = intel_runtime_pm_get(gt->uncore->rpm);
+
+	i915_perf_fini(gt->i915);
+	intel_engines_release(gt);
+	intel_engines_free(gt);
+
+	mutex_lock(&gt->ccs.mutex);
+	engine_update_mask(gt, val);
+	mutex_unlock(&gt->ccs.mutex);
+
+	intel_engines_init_mmio(gt);
+	i915_perf_init(gt->i915);
+	intel_engines_init(gt);
+
+	gt->i915->uabi_engines = RB_ROOT;
+	intel_engines_driver_register(gt->i915);
+
+	intel_runtime_pm_put(gt->uncore->rpm, wakeref);
+
+	intel_engines_add_sysfs(gt->i915);
+
+	return count;
+}
+static DEVICE_ATTR_RW(ccs_mode);
+
 void intel_gt_sysfs_ccs_init(struct intel_gt *gt)
 {
 	int err;
@@ -155,4 +252,15 @@ void intel_gt_sysfs_ccs_init(struct intel_gt *gt)
 	err = sysfs_create_file(&gt->sysfs_gt, &dev_attr_num_cslices.attr);
 	if (err)
 		gt_dbg(gt, "failed to create sysfs num_cslices files\n");
+
+	/*
+	 * Do not create the ccs_mode file for non DG2 platforms
+	 * because they don't need it as they have only one CCS engine
+	 */
+	if (!IS_DG2(gt->i915))
+		return;
+
+	err = sysfs_create_file(&gt->sysfs_gt, &dev_attr_ccs_mode.attr);
+	if (err)
+		gt_dbg(gt, "failed to create sysfs ccs_mode files\n");
 }
-- 
2.45.2