> -----Original Message-----
> From: Deak, Imre <imre.deak@xxxxxxxxx>
> Sent: Wednesday, June 26, 2024 8:08 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Kahola, Mika <mika.kahola@xxxxxxxxx>
> Subject: [PATCH] drm/i915/mtl: Skip PLL state verification in TBT mode
>
> In TBT-alt mode the driver doesn't program the PHY's PLL, which is handled instead by
> Thunderbolt driver/FW components, hence the PLL's HW vs. SW state verification
> should be skipped. During HW readout set a flag in the PLL state if the port was at the
> moment in TBT-alt mode and skip the verification of PLL parameters in this case.
>
> Fixes: 45fe957ae769 ("drm/i915/display: Add compare config for MTL+ platforms")
> Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
Reviewed-by: Mika Kahola <mika.kahola@xxxxxxxxx>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 13 +++++++++----
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++-----
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
> 3 files changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 41f684c970dcf..4a6c3040ca15e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3279,6 +3279,10 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder
> *encoder, {
> pll_state->use_c10 = false;
>
> + pll_state->tbt_mode =
> intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
> + if (pll_state->tbt_mode)
> + return;
> +
> if (intel_encoder_is_c10phy(encoder)) {
> intel_c10pll_readout_hw_state(encoder, &pll_state->c10);
> pll_state->use_c10 = true;
> @@ -3325,6 +3329,8 @@ static bool mtl_compare_hw_state_c20(const struct
> intel_c20pll_state *a, bool intel_cx0pll_compare_hw_state(const struct
> intel_cx0pll_state *a,
> const struct intel_cx0pll_state *b) {
> + if (a->tbt_mode || b->tbt_mode)
> + return true;
>
> if (a->use_c10 != b->use_c10)
> return false;
> @@ -3420,12 +3426,11 @@ void intel_cx0pll_state_verify(struct intel_atomic_state
> *state,
> return;
>
> encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> -
> - if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
> - return;
> -
> intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state);
>
> + if (mpll_hw_state.tbt_mode)
> + return;
> +
> if (intel_encoder_is_c10phy(encoder))
> intel_c10pll_state_verify(new_crtc_state, crtc, encoder,
> &mpll_hw_state.c10);
> else
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bb13a3ca8c7c9..c5510d5bbe696 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4024,14 +4024,12 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
> static void mtl_ddi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state) {
> - struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + intel_cx0pll_readout_hw_state(encoder,
> +&crtc_state->dpll_hw_state.cx0pll);
>
> - if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
> + if (crtc_state->dpll_hw_state.cx0pll.tbt_mode)
> crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
> - } else {
> - intel_cx0pll_readout_hw_state(encoder, &crtc_state-
> >dpll_hw_state.cx0pll);
> + else
> crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> &crtc_state->dpll_hw_state.cx0pll);
> - }
>
> intel_ddi_get_config(encoder, crtc_state); } diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 36baed75b89ab..6af325b8e27dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -265,6 +265,7 @@ struct intel_cx0pll_state {
> };
> bool ssc_enabled;
> bool use_c10;
> + bool tbt_mode;
> };
>
> struct intel_dpll_hw_state {
> --
> 2.43.3
