The HDMI PLL programming involves pre-calculated values for specific frequencies and an algorithm to compute values for other frequencies. While the algorithm itself wasn't part of the driver, tables were added based on it for known modes. Some HDMI modes were pruned due to lack of support (for example issues [1],[2], and [3]). This series adds the algorithm for computing HDMI PLLs for SNPS/C10PHY to work with all modes supported by the hardware. The original algorithm uses floating-point math, which has been converted to integers while preserving precision. As a result, the values in the existing computable tables are very close but not exact. Testing with DG2 and MTL on various panels revealed no issues. [1] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9722 [2] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10654 [3] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10956 Ankit Nautiyal (5): drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2 drm/i915/snps_phy: Use HDMI PLL algorithm for DG2 drm/i915/cx0_phy_regs: Add C10 registers bits drm/i915/pll_algorithm: Compute C10 HDMI PLLs with algorithm drm/xe: Add intel_pll_algorithm in Makefile drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_cx0_phy.c | 15 + .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 24 ++ .../drm/i915/display/intel_pll_algorithm.c | 317 ++++++++++++++++++ .../drm/i915/display/intel_pll_algorithm.h | 41 +++ drivers/gpu/drm/i915/display/intel_snps_phy.c | 20 +- drivers/gpu/drm/xe/Makefile | 1 + 7 files changed, 407 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_pll_algorithm.c create mode 100644 drivers/gpu/drm/i915/display/intel_pll_algorithm.h -- 2.40.1
