On Tue, Jun 25, 2024 at 02:05:39PM -0000, Patchwork wrote: > == Series Details == > > Series: drm/i915: Enable CCS+10bpc and CCS+async flips > URL : https://patchwork.freedesktop.org/series/135306/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_14995_full -> Patchwork_135306v1_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_135306v1_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_135306v1_full, please notify your bug team (I915-ci-infra@xxxxxxxxxxxxxxxxxxxxx) to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135306v1/index.html > > Participating hosts (9 -> 9) > ------------------------------ > > No changes in participating hosts > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_135306v1_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@i915_hangman@gt-error-state-capture@ccs0: > - shard-dg2: [PASS][1] -> [INCOMPLETE][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14995/shard-dg2-10/igt@i915_hangman@gt-error-state-capture@xxxxxxxxx > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135306v1/shard-dg2-5/igt@i915_hangman@gt-error-state-capture@xxxxxxxxx > > * igt@i915_hangman@gt-error-state-capture@vcs1: > - shard-dg1: [PASS][3] -> [INCOMPLETE][4] > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14995/shard-dg1-17/igt@i915_hangman@gt-error-state-capture@xxxxxxxxx > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135306v1/shard-dg1-13/igt@i915_hangman@gt-error-state-capture@xxxxxxxxx > > * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-1: > - shard-rkl: NOTRUN -> [FAIL][5] +1 other test fail Hmm. Looks like IGT will need specific handling for 10bpc in order to make the clear color work properly. -- Ville Syrjälä Intel
