> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@xxxxxxxxx>
> Sent: Thursday, June 13, 2024 3:02 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Manna, Animesh <animesh.manna@xxxxxxxxx>; Kahola, Mika
> <mika.kahola@xxxxxxxxx>; Hogander, Jouni <jouni.hogander@xxxxxxxxx>
> Subject: [PATCH v8 08/20] drm/i915/psr: Add new debug bit to disable Panel
> Replay
>
> Add new debug bit to be used with i915_edp_psr_debug debugfs interface.
> This can be used to disable Panel Replay.
>
> v2: ensure that fastset is performed when the bit changes
>
> Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
Reviewed-by: Animesh Manna <animesh.manna@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++---
> 2 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 4ee760bd26f7..b8980e8b4c36 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1697,6 +1697,7 @@ struct intel_psr {
> #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
> #define I915_PSR_DEBUG_IRQ 0x10
> #define I915_PSR_DEBUG_SU_REGION_ET_DISABLE 0x20
> +#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
>
> u32 debug;
> bool sink_support;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7300d04806cd..cd77cfeba679 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -249,7 +249,8 @@ static bool panel_replay_global_enabled(struct
> intel_dp *intel_dp) {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> - if (i915->display.params.enable_psr != -1)
> + if ((i915->display.params.enable_psr != -1) ||
> + (intel_dp->psr.debug &
> I915_PSR_DEBUG_PANEL_REPLAY_DISABLE))
> return false;
> return true;
> }
> @@ -2788,11 +2789,13 @@ int intel_psr_debug_set(struct intel_dp
> *intel_dp, u64 val) {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
> - const u32 disable_bits = val &
> I915_PSR_DEBUG_SU_REGION_ET_DISABLE;
> + const u32 disable_bits = val &
> (I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
> +
> I915_PSR_DEBUG_PANEL_REPLAY_DISABLE);
> u32 old_mode, old_disable_bits;
> int ret;
>
> if (val & ~(I915_PSR_DEBUG_IRQ |
> I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
> + I915_PSR_DEBUG_PANEL_REPLAY_DISABLE |
> I915_PSR_DEBUG_MODE_MASK) ||
> mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
> drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n",
> val); @@ -2805,7 +2808,9 @@ int intel_psr_debug_set(struct intel_dp
> *intel_dp, u64 val)
>
> old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
> old_disable_bits = intel_dp->psr.debug &
> - I915_PSR_DEBUG_SU_REGION_ET_DISABLE;
> + (I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
> + I915_PSR_DEBUG_PANEL_REPLAY_DISABLE);
> +
> intel_dp->psr.debug = val;
>
> /*
> --
> 2.34.1
