From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> DSB_STATUS bit 16 is supposed to be a sticky bit informing us whether the DSB was idle or not when the pipe's delayed vblank (when double buffered registers latch) occurred. Unfortunately it turns out this is a level triggred signal, ie. the bit will be set whenever the DSB is busy during the scanline window between start of delayed vblank and vtotal. Try to document that fact by renaming the bit. Sadly this also thwarts my plan to use this bit to sanity check that the (to be introduced) DSB based vblank evasion did its job correctly. That would require an edge triggered signal instead. So looks like we'll have to rely mostly on luck instead :( Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_dsb_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb_regs.h b/drivers/gpu/drm/i915/display/intel_dsb_regs.h index 9c2664ff519a..cb6e0e5624a6 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dsb_regs.h @@ -45,7 +45,7 @@ #define DSB_TLBTRANS_SM_STATE_MASK REG_GENMASK(21, 20) #define DSB_SAFE_WINDOW REG_BIT(19) #define DSB_POINTERS_SM_STATE_MASK REG_GENMASK(18, 17) -#define DSB_BUSY_ON_DELAYED_VBLANK REG_BIT(16) +#define DSB_BUSY_DURING_DELAYED_VBLANK REG_BIT(16) #define DSB_MMIO_ARB_SM_STATE_MASK REG_GENMASK(15, 13) #define DSB_MMIO_INST_SM_STATE_MASK REG_GENMASK(11, 7) #define DSB_RESET_SM_STATE_MASK REG_GENMASK(5, 4) -- 2.44.2
