> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Mitul > Golani > Sent: Monday, June 10, 2024 12:52 PM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@xxxxxxxxx> > Subject: [PATCH v16 2/9] drm/i915: Separate VRR related register definitions > > Move VRR related register definitions to a separate file called intel_vrr_regs.h. > > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@xxxxxxxxx> > Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx> > --- Reviewed-by: Arun R Murthy <arun.r.murthy@xxxxxxxxx> Thanks and Regards, Arun R Murthy -------------------- > drivers/gpu/drm/i915/display/intel_vrr.c | 1 + > drivers/gpu/drm/i915/display/intel_vrr_regs.h | 111 ++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 100 ---------------- > 3 files changed, 112 insertions(+), 100 deletions(-) create mode 100644 > drivers/gpu/drm/i915/display/intel_vrr_regs.h > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c > b/drivers/gpu/drm/i915/display/intel_vrr.c > index 5f3657aa8313..871e6e6a184a 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -9,6 +9,7 @@ > #include "intel_de.h" > #include "intel_display_types.h" > #include "intel_vrr.h" > +#include "intel_vrr_regs.h" > #include "intel_dp.h" > > bool intel_vrr_is_capable(struct intel_connector *connector) diff --git > a/drivers/gpu/drm/i915/display/intel_vrr_regs.h > b/drivers/gpu/drm/i915/display/intel_vrr_regs.h > new file mode 100644 > index 000000000000..c3237d5c38df > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h > @@ -0,0 +1,111 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2024 Intel Corporation > + */ > + > +#ifndef __INTEL_VRR_REGS_H__ > +#define __INTEL_VRR_REGS_H__ > + > +#include "intel_display_reg_defs.h" > + > +/* VRR registers */ > +#define _TRANS_VRR_CTL_A 0x60420 > +#define _TRANS_VRR_CTL_B 0x61420 > +#define _TRANS_VRR_CTL_C 0x62420 > +#define _TRANS_VRR_CTL_D 0x63420 > +#define TRANS_VRR_CTL(dev_priv, trans) > _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) > +#define VRR_CTL_VRR_ENABLE REG_BIT(31) > +#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) > +#define VRR_CTL_FLIP_LINE_EN REG_BIT(29) > +#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) > +#define VRR_CTL_PIPELINE_FULL(x) > REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) > +#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) > +#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) > +#define XELPD_VRR_CTL_VRR_GUARDBAND(x) > REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) > + > +#define _TRANS_VRR_VMAX_A 0x60424 > +#define _TRANS_VRR_VMAX_B 0x61424 > +#define _TRANS_VRR_VMAX_C 0x62424 > +#define _TRANS_VRR_VMAX_D 0x63424 > +#define TRANS_VRR_VMAX(dev_priv, trans) > _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A) > +#define VRR_VMAX_MASK REG_GENMASK(19, 0) > + > +#define _TRANS_VRR_VMIN_A 0x60434 > +#define _TRANS_VRR_VMIN_B 0x61434 > +#define _TRANS_VRR_VMIN_C 0x62434 > +#define _TRANS_VRR_VMIN_D 0x63434 > +#define TRANS_VRR_VMIN(dev_priv, trans) > _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A) > +#define VRR_VMIN_MASK REG_GENMASK(15, 0) > + > +#define _TRANS_VRR_VMAXSHIFT_A 0x60428 > +#define _TRANS_VRR_VMAXSHIFT_B 0x61428 > +#define _TRANS_VRR_VMAXSHIFT_C 0x62428 > +#define _TRANS_VRR_VMAXSHIFT_D 0x63428 > +#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) > _MMIO_TRANS2(dev_priv, trans, \ > + _TRANS_VRR_VMAXSHIFT_A) > +#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, > 16) > +#define VRR_VMAXSHIFT_DEC REG_BIT(16) > +#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) > + > +#define _TRANS_VRR_STATUS_A 0x6042c > +#define _TRANS_VRR_STATUS_B 0x6142c > +#define _TRANS_VRR_STATUS_C 0x6242c > +#define _TRANS_VRR_STATUS_D 0x6342c > +#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, _TRANS_VRR_STATUS_A) > +#define VRR_STATUS_VMAX_REACHED REG_BIT(31) > +#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) > +#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) > +#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) > +#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) > +#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) > +#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, > 20) > +#define STATUS_FSM_IDLE > REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) > +#define STATUS_FSM_WAIT_TILL_FDB > REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) > +#define STATUS_FSM_WAIT_TILL_FS > REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) > +#define STATUS_FSM_WAIT_TILL_FLIP > REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) > +#define STATUS_FSM_PIPELINE_FILL > REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) > +#define STATUS_FSM_ACTIVE > REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) > +#define STATUS_FSM_LEGACY_VBLANK > REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) > + > +#define _TRANS_VRR_VTOTAL_PREV_A 0x60480 > +#define _TRANS_VRR_VTOTAL_PREV_B 0x61480 > +#define _TRANS_VRR_VTOTAL_PREV_C 0x62480 > +#define _TRANS_VRR_VTOTAL_PREV_D 0x63480 > +#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) > _MMIO_TRANS2(dev_priv, trans, \ > + > _TRANS_VRR_VTOTAL_PREV_A) > +#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) > +#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) > +#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) > +#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) > + > +#define _TRANS_VRR_FLIPLINE_A 0x60438 > +#define _TRANS_VRR_FLIPLINE_B 0x61438 > +#define _TRANS_VRR_FLIPLINE_C 0x62438 > +#define _TRANS_VRR_FLIPLINE_D 0x63438 > +#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, \ > + _TRANS_VRR_FLIPLINE_A) > +#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) > + > +#define _TRANS_VRR_STATUS2_A 0x6043c > +#define _TRANS_VRR_STATUS2_B 0x6143c > +#define _TRANS_VRR_STATUS2_C 0x6243c > +#define _TRANS_VRR_STATUS2_D 0x6343c > +#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, _TRANS_VRR_STATUS2_A) > +#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) > + > +#define _TRANS_PUSH_A 0x60a70 > +#define _TRANS_PUSH_B 0x61a70 > +#define _TRANS_PUSH_C 0x62a70 > +#define _TRANS_PUSH_D 0x63a70 > +#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, _TRANS_PUSH_A) > +#define TRANS_PUSH_EN REG_BIT(31) > +#define TRANS_PUSH_SEND REG_BIT(30) > + > +#define _TRANS_VRR_VSYNC_A 0x60078 > +#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, _TRANS_VRR_VSYNC_A) > +#define VRR_VSYNC_END_MASK REG_GENMASK(28, > 16) > +#define VRR_VSYNC_END(vsync_end) > REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) > +#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) > +#define VRR_VSYNC_START(vsync_start) > REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) > + > +#endif /* __INTEL_VRR_REGS__ */ > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h index 3fbf639e6aa0..df58cf38e144 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1147,106 +1147,6 @@ > #define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), > _PIPEASRC) > #define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), > _TRANS_MULT_A) > > -/* VRR registers */ > -#define _TRANS_VRR_CTL_A 0x60420 > -#define _TRANS_VRR_CTL_B 0x61420 > -#define _TRANS_VRR_CTL_C 0x62420 > -#define _TRANS_VRR_CTL_D 0x63420 > -#define TRANS_VRR_CTL(dev_priv, trans) > _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) > -#define VRR_CTL_VRR_ENABLE REG_BIT(31) > -#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) > -#define VRR_CTL_FLIP_LINE_EN REG_BIT(29) > -#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) > -#define VRR_CTL_PIPELINE_FULL(x) > REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) > -#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) > -#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) > -#define XELPD_VRR_CTL_VRR_GUARDBAND(x) > REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) > - > -#define _TRANS_VRR_VMAX_A 0x60424 > -#define _TRANS_VRR_VMAX_B 0x61424 > -#define _TRANS_VRR_VMAX_C 0x62424 > -#define _TRANS_VRR_VMAX_D 0x63424 > -#define TRANS_VRR_VMAX(dev_priv, trans) > _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A) > -#define VRR_VMAX_MASK REG_GENMASK(19, 0) > - > -#define _TRANS_VRR_VMIN_A 0x60434 > -#define _TRANS_VRR_VMIN_B 0x61434 > -#define _TRANS_VRR_VMIN_C 0x62434 > -#define _TRANS_VRR_VMIN_D 0x63434 > -#define TRANS_VRR_VMIN(dev_priv, trans) > _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A) > -#define VRR_VMIN_MASK REG_GENMASK(15, 0) > - > -#define _TRANS_VRR_VMAXSHIFT_A 0x60428 > -#define _TRANS_VRR_VMAXSHIFT_B 0x61428 > -#define _TRANS_VRR_VMAXSHIFT_C 0x62428 > -#define _TRANS_VRR_VMAXSHIFT_D 0x63428 > -#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) > _MMIO_TRANS2(dev_priv, trans, \ > - _TRANS_VRR_VMAXSHIFT_A) > -#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, > 16) > -#define VRR_VMAXSHIFT_DEC REG_BIT(16) > -#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) > - > -#define _TRANS_VRR_STATUS_A 0x6042c > -#define _TRANS_VRR_STATUS_B 0x6142c > -#define _TRANS_VRR_STATUS_C 0x6242c > -#define _TRANS_VRR_STATUS_D 0x6342c > -#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, _TRANS_VRR_STATUS_A) > -#define VRR_STATUS_VMAX_REACHED REG_BIT(31) > -#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) > -#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) > -#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) > -#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) > -#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) > -#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, > 20) > -#define STATUS_FSM_IDLE > REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) > -#define STATUS_FSM_WAIT_TILL_FDB > REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) > -#define STATUS_FSM_WAIT_TILL_FS > REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) > -#define STATUS_FSM_WAIT_TILL_FLIP > REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) > -#define STATUS_FSM_PIPELINE_FILL > REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) > -#define STATUS_FSM_ACTIVE > REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) > -#define STATUS_FSM_LEGACY_VBLANK > REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) > - > -#define _TRANS_VRR_VTOTAL_PREV_A 0x60480 > -#define _TRANS_VRR_VTOTAL_PREV_B 0x61480 > -#define _TRANS_VRR_VTOTAL_PREV_C 0x62480 > -#define _TRANS_VRR_VTOTAL_PREV_D 0x63480 > -#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) > _MMIO_TRANS2(dev_priv, trans, \ > - > _TRANS_VRR_VTOTAL_PREV_A) > -#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) > -#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) > -#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) > -#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) > - > -#define _TRANS_VRR_FLIPLINE_A 0x60438 > -#define _TRANS_VRR_FLIPLINE_B 0x61438 > -#define _TRANS_VRR_FLIPLINE_C 0x62438 > -#define _TRANS_VRR_FLIPLINE_D 0x63438 > -#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, \ > - _TRANS_VRR_FLIPLINE_A) > -#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) > - > -#define _TRANS_VRR_STATUS2_A 0x6043c > -#define _TRANS_VRR_STATUS2_B 0x6143c > -#define _TRANS_VRR_STATUS2_C 0x6243c > -#define _TRANS_VRR_STATUS2_D 0x6343c > -#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, _TRANS_VRR_STATUS2_A) > -#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) > - > -#define _TRANS_PUSH_A 0x60a70 > -#define _TRANS_PUSH_B 0x61a70 > -#define _TRANS_PUSH_C 0x62a70 > -#define _TRANS_PUSH_D 0x63a70 > -#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, _TRANS_PUSH_A) > -#define TRANS_PUSH_EN REG_BIT(31) > -#define TRANS_PUSH_SEND REG_BIT(30) > - > -#define _TRANS_VRR_VSYNC_A 0x60078 > -#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, _TRANS_VRR_VSYNC_A) > -#define VRR_VSYNC_END_MASK REG_GENMASK(28, > 16) > -#define VRR_VSYNC_END(vsync_end) > REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) > -#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) > -#define VRR_VSYNC_START(vsync_start) > REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) > - > /* VGA port control */ > #define ADPA _MMIO(0x61100) > #define PCH_ADPA _MMIO(0xe1100) > -- > 2.45.2
