Hi Suraj, kernel test robot noticed the following build errors: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.10-rc2 next-20240606] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Suraj-Kandpal/drm-i915-psr-Add-return-bool-value-for-hsw_activate_psr1/20240606-163351 base: git://anongit.freedesktop.org/drm-intel for-linux-next patch link: https://lore.kernel.org/r/20240606082926.1816416-4-suraj.kandpal%40intel.com patch subject: [PATCH 2/2] drm/i915/psr: Implment WA to help reach PC10 config: microblaze-allmodconfig (https://download.01.org/0day-ci/archive/20240607/202406070543.soJpPCOs-lkp@xxxxxxxxx/config) compiler: microblaze-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240607/202406070543.soJpPCOs-lkp@xxxxxxxxx/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@xxxxxxxxx> | Closes: https://lore.kernel.org/oe-kbuild-all/202406070543.soJpPCOs-lkp@xxxxxxxxx/ All errors (new ones prefixed by >>): In file included from drivers/gpu/drm/i915/display/intel_psr.c:35: drivers/gpu/drm/i915/display/intel_psr.c: In function 'intel_psr_check_delayed_vblank_limit': >> drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg.h:4158:62: error: 'dev_priv' undeclared (first use in this function); did you mean 'dev_crit'? 4158 | #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY) | ^~~~~~~~ drivers/gpu/drm/i915/display/intel_de.h:31:69: note: in definition of macro 'intel_de_read' 31 | #define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), __VA_ARGS__) | ^~~~~~~~~~~ drivers/gpu/drm/xe/compat-i915-headers/../../i915/display/intel_display_reg_defs.h:42:49: note: in expansion of macro '_MMIO' 42 | #define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \ | ^~~~~ drivers/gpu/drm/i915/display/intel_display_device.h:185:42: note: in expansion of macro '__to_intel_display' 185 | #define DISPLAY_INFO(i915) (__to_intel_display(i915)->info.__device_info) | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/xe/compat-i915-headers/../../i915/display/intel_display_reg_defs.h:42:55: note: in expansion of macro 'DISPLAY_INFO' 42 | #define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \ | ^~~~~~~~~~~~ drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg.h:4158:49: note: in expansion of macro '_MMIO_TRANS2' 4158 | #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY) | ^~~~~~~~~~~~ drivers/gpu/drm/i915/display/intel_psr.c:817:36: note: in expansion of macro 'TRANS_SET_CONTEXT_LATENCY' 817 | return intel_de_read(i915, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder)) >= 6; | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg.h:4158:62: note: each undeclared identifier is reported only once for each function it appears in 4158 | #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY) | ^~~~~~~~ drivers/gpu/drm/i915/display/intel_de.h:31:69: note: in definition of macro 'intel_de_read' 31 | #define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), __VA_ARGS__) | ^~~~~~~~~~~ drivers/gpu/drm/xe/compat-i915-headers/../../i915/display/intel_display_reg_defs.h:42:49: note: in expansion of macro '_MMIO' 42 | #define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \ | ^~~~~ drivers/gpu/drm/i915/display/intel_display_device.h:185:42: note: in expansion of macro '__to_intel_display' 185 | #define DISPLAY_INFO(i915) (__to_intel_display(i915)->info.__device_info) | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/xe/compat-i915-headers/../../i915/display/intel_display_reg_defs.h:42:55: note: in expansion of macro 'DISPLAY_INFO' 42 | #define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \ | ^~~~~~~~~~~~ drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg.h:4158:49: note: in expansion of macro '_MMIO_TRANS2' 4158 | #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY) | ^~~~~~~~~~~~ drivers/gpu/drm/i915/display/intel_psr.c:817:36: note: in expansion of macro 'TRANS_SET_CONTEXT_LATENCY' 817 | return intel_de_read(i915, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder)) >= 6; | ^~~~~~~~~~~~~~~~~~~~~~~~~ >> drivers/gpu/drm/i915/display/intel_psr.c:815:66: error: parameter 'cpu_transcoder' set but not used [-Werror=unused-but-set-parameter] 815 | enum transcoder cpu_transcoder) | ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~ drivers/gpu/drm/i915/display/intel_psr.c: In function 'intel_psr_is_dpkgc_configured': >> drivers/gpu/drm/i915/display/intel_psr.c:822:36: error: 'LNL_PKG_C_LATENCY' undeclared (first use in this function) 822 | return intel_de_read(i915, LNL_PKG_C_LATENCY) == U32_MAX; | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/display/intel_de.h:31:69: note: in definition of macro 'intel_de_read' 31 | #define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), __VA_ARGS__) | ^~~~~~~~~~~ drivers/gpu/drm/i915/display/intel_psr.c: In function 'intel_psr_is_dc5_entry_possible': >> drivers/gpu/drm/i915/display/intel_psr.c:835:26: error: 'struct drm_crtc' has no member named 'active' 835 | if (!crtc->active) | ^~ >> drivers/gpu/drm/i915/display/intel_psr.c:842:69: error: '_encoder' undeclared (first use in this function); did you mean 'encoder'? 842 | struct intel_dp *intel_dp = enc_to_intel_dp(_encoder); | ^~~~~~~~ | encoder drivers/gpu/drm/i915/display/intel_psr.c: In function 'wa_16023497226_check': >> drivers/gpu/drm/i915/display/intel_psr.c:861:13: error: implicit declaration of function 'is_dpkg_c_configured' [-Werror=implicit-function-declaration] 861 | if (is_dpkg_c_configured(i915)) { | ^~~~~~~~~~~~~~~~~~~~ >> drivers/gpu/drm/i915/display/intel_psr.c:866:35: error: implicit declaration of function 'is_dc5_entry_possible'; did you mean 'intel_psr_is_dc5_entry_possible'? [-Werror=implicit-function-declaration] 866 | else if (!psr1 && is_dc5_entry_possible(i915)) | ^~~~~~~~~~~~~~~~~~~~~ | intel_psr_is_dc5_entry_possible drivers/gpu/drm/i915/display/intel_psr.c: In function 'intel_psr_check_delayed_vblank_limit': drivers/gpu/drm/i915/display/intel_psr.c:818:1: warning: control reaches end of non-void function [-Wreturn-type] 818 | } | ^ drivers/gpu/drm/i915/display/intel_psr.c: At top level: >> drivers/gpu/drm/i915/display/intel_psr.c:820:13: error: 'intel_psr_is_dpkgc_configured' defined but not used [-Werror=unused-function] 820 | static bool intel_psr_is_dpkgc_configured(struct drm_i915_private *i915) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors vim +4158 drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg.h dae847991a4327 Paulo Zanoni 2012-10-15 4153 1d53ccdc400c87 José Roberto de Souza 2021-06-16 4154 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C 1d53ccdc400c87 José Roberto de Souza 2021-06-16 4155 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C 1d53ccdc400c87 José Roberto de Souza 2021-06-16 4156 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C 1d53ccdc400c87 José Roberto de Souza 2021-06-16 4157 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C 407569ff790979 Jani Nikula 2024-04-23 @4158 #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY) 1d53ccdc400c87 José Roberto de Souza 2021-06-16 4159 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) 1d53ccdc400c87 José Roberto de Souza 2021-06-16 4160 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) 1d53ccdc400c87 José Roberto de Souza 2021-06-16 4161 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
