On Tue, Jun 04, 2024 at 06:26:08PM +0300, Jani Nikula wrote: > Avoid the implicit dev_priv local variable use, and pass dev_priv > explicitly to the PIPE_DATA_M1 register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > > Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_display.c | 6 ++++-- > drivers/gpu/drm/i915/display/intel_fdi.c | 6 +++--- > drivers/gpu/drm/i915/gvt/display.c | 8 ++++---- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- > 5 files changed, 16 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 241121b0b3ff..7fd65e3b018d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2641,7 +2641,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, > > if (DISPLAY_VER(dev_priv) >= 5) > intel_set_m_n(dev_priv, m_n, > - PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), > + PIPE_DATA_M1(dev_priv, transcoder), > + PIPE_DATA_N1(transcoder), > PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); > else > intel_set_m_n(dev_priv, m_n, > @@ -3337,7 +3338,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, > > if (DISPLAY_VER(dev_priv) >= 5) > intel_get_m_n(dev_priv, m_n, > - PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), > + PIPE_DATA_M1(dev_priv, transcoder), > + PIPE_DATA_N1(transcoder), > PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); > else > intel_get_m_n(dev_priv, m_n, > diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c > index 8b17b8ad71c3..007e0f9e9304 100644 > --- a/drivers/gpu/drm/i915/display/intel_fdi.c > +++ b/drivers/gpu/drm/i915/display/intel_fdi.c > @@ -514,7 +514,7 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc, > * detection works. > */ > intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), > - intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); > + intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); > > /* FDI needs bits from pipe first */ > assert_transcoder_enabled(dev_priv, crtc_state->cpu_transcoder); > @@ -616,7 +616,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, > * detection works. > */ > intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), > - intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); > + intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); > > /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit > for train result */ > @@ -754,7 +754,7 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, > * detection works. > */ > intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), > - intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); > + intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); > > /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit > for train result */ > diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c > index 3681dca165c6..ce6f20b1dabc 100644 > --- a/drivers/gpu/drm/i915/gvt/display.c > +++ b/drivers/gpu/drm/i915/gvt/display.c > @@ -261,8 +261,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) > * DP link clk 1620 MHz and non-constant_n. > * TODO: calculate DP link symbol clk and stream clk m/n. > */ > - vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64); > - vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; > + vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); > + vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; > vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; > vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; > vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; > @@ -395,8 +395,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) > * DP link clk 1620 MHz and non-constant_n. > * TODO: calculate DP link symbol clk and stream clk m/n. > */ > - vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64); > - vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; > + vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); > + vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; > vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; > vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; > vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 62cb456568e5..96bfa5620989 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2379,7 +2379,7 @@ > #define _PIPEB_LINK_M2 0x61048 > #define _PIPEB_LINK_N2 0x6104c > > -#define PIPE_DATA_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1) > +#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1) > #define PIPE_DATA_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1) > #define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) > #define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) > diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > index ba3f734ced0b..977d695fbdff 100644 > --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > @@ -266,7 +266,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) > MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP)); > MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP)); > MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP)); > - MMIO_D(PIPE_DATA_M1(TRANSCODER_A)); > + MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A)); > MMIO_D(PIPE_DATA_N1(TRANSCODER_A)); > MMIO_D(PIPE_DATA_M2(TRANSCODER_A)); > MMIO_D(PIPE_DATA_N2(TRANSCODER_A)); > @@ -274,7 +274,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) > MMIO_D(PIPE_LINK_N1(TRANSCODER_A)); > MMIO_D(PIPE_LINK_M2(TRANSCODER_A)); > MMIO_D(PIPE_LINK_N2(TRANSCODER_A)); > - MMIO_D(PIPE_DATA_M1(TRANSCODER_B)); > + MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B)); > MMIO_D(PIPE_DATA_N1(TRANSCODER_B)); > MMIO_D(PIPE_DATA_M2(TRANSCODER_B)); > MMIO_D(PIPE_DATA_N2(TRANSCODER_B)); > @@ -282,7 +282,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) > MMIO_D(PIPE_LINK_N1(TRANSCODER_B)); > MMIO_D(PIPE_LINK_M2(TRANSCODER_B)); > MMIO_D(PIPE_LINK_N2(TRANSCODER_B)); > - MMIO_D(PIPE_DATA_M1(TRANSCODER_C)); > + MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C)); > MMIO_D(PIPE_DATA_N1(TRANSCODER_C)); > MMIO_D(PIPE_DATA_M2(TRANSCODER_C)); > MMIO_D(PIPE_DATA_N2(TRANSCODER_C)); > @@ -290,7 +290,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) > MMIO_D(PIPE_LINK_N1(TRANSCODER_C)); > MMIO_D(PIPE_LINK_M2(TRANSCODER_C)); > MMIO_D(PIPE_LINK_N2(TRANSCODER_C)); > - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP)); > + MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP)); > MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP)); > MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP)); > MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP)); > -- > 2.39.2 >
