On Tue, Jun 04, 2024 at 06:25:46PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the DSPFW3 register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/i9xx_wm.c | 27 ++++++++++---------
> .../drm/i915/display/intel_display_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 3 files changed, 17 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 1e11d66d1a7e..3fe24bae0728 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -149,14 +149,14 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
> intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
> intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
> } else if (IS_PINEVIEW(dev_priv)) {
> - val = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> + val = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
> was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
> if (enable)
> val |= PINEVIEW_SELF_REFRESH_EN;
> else
> val &= ~PINEVIEW_SELF_REFRESH_EN;
> - intel_uncore_write(&dev_priv->uncore, DSPFW3, val);
> - intel_uncore_posting_read(&dev_priv->uncore, DSPFW3);
> + intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), val);
> + intel_uncore_posting_read(&dev_priv->uncore, DSPFW3(dev_priv));
> } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
> was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
> val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
> @@ -668,7 +668,8 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
> &pnv_cursor_wm,
> pnv_display_wm.fifo_size,
> 4, latency->cursor_sr);
> - intel_uncore_rmw(&dev_priv->uncore, DSPFW3, DSPFW_CURSOR_SR_MASK,
> + intel_uncore_rmw(&dev_priv->uncore, DSPFW3(dev_priv),
> + DSPFW_CURSOR_SR_MASK,
> FW_WM(wm, CURSOR_SR));
>
> /* Display HPLL off SR */
> @@ -676,17 +677,18 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
> &pnv_display_hplloff_wm,
> pnv_display_hplloff_wm.fifo_size,
> cpp, latency->display_hpll_disable);
> - intel_uncore_rmw(&dev_priv->uncore, DSPFW3, DSPFW_HPLL_SR_MASK, FW_WM(wm, HPLL_SR));
> + intel_uncore_rmw(&dev_priv->uncore, DSPFW3(dev_priv),
> + DSPFW_HPLL_SR_MASK, FW_WM(wm, HPLL_SR));
>
> /* cursor HPLL off SR */
> wm = intel_calculate_wm(dev_priv, pixel_rate,
> &pnv_cursor_hplloff_wm,
> pnv_display_hplloff_wm.fifo_size,
> 4, latency->cursor_hpll_disable);
> - reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> + reg = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
> reg &= ~DSPFW_HPLL_CURSOR_MASK;
> reg |= FW_WM(wm, HPLL_CURSOR);
> - intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
> + intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), reg);
> drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
>
> intel_set_memory_cxsr(dev_priv, true);
> @@ -732,7 +734,7 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
> FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
> FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
> FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
> - intel_uncore_write(&dev_priv->uncore, DSPFW3,
> + intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv),
> (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
> FW_WM(wm->sr.cursor, CURSOR_SR) |
> FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
> @@ -779,7 +781,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
> FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
> FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
> FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
> - intel_uncore_write(&dev_priv->uncore, DSPFW3,
> + intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv),
> FW_WM(wm->sr.cursor, CURSOR_SR));
>
> if (IS_CHERRYVIEW(dev_priv)) {
> @@ -2076,7 +2078,8 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
> FW_WM(8, CURSORA) |
> FW_WM(8, PLANEC_OLD));
> /* update cursor SR watermark */
> - intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
> + intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv),
> + FW_WM(cursor_sr, CURSOR_SR));
>
> if (cxsr_enabled)
> intel_set_memory_cxsr(dev_priv, true);
> @@ -3537,7 +3540,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
> wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
> wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
>
> - tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> + tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
> wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
> wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
> wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
> @@ -3574,7 +3577,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
> wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
> wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
>
> - tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> + tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
> wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
>
> if (IS_CHERRYVIEW(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 86d9900c40af..b538a8204124 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -77,7 +77,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
> else if (IS_I915GM(dev_priv))
> sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
> else if (IS_PINEVIEW(dev_priv))
> - sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
> + sr_enabled = intel_de_read(dev_priv, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8b642cb0d9b7..05e0013813f8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2046,7 +2046,7 @@
> #define DSPFW_SPRITEA_SHIFT 0
> #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
> #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
> -#define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
> +#define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
> #define DSPFW_HPLL_SR_EN (1 << 31)
> #define PINEVIEW_SELF_REFRESH_EN (1 << 30)
> #define DSPFW_CURSOR_SR_SHIFT 24
> --
> 2.39.2
>
