On Tue, Jun 04, 2024 at 06:25:33PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PFIT_CONTROL register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 11 ++++++-----
> drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
> drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 4 files changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e7ee4970e306..49672694293f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1861,12 +1861,13 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
> * according to register description and PRM.
> */
> drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
> + intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE);
> assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
>
> intel_de_write(dev_priv, PFIT_PGM_RATIOS,
> crtc_state->gmch_pfit.pgm_ratios);
> - intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
> + intel_de_write(dev_priv, PFIT_CONTROL(dev_priv),
> + crtc_state->gmch_pfit.control);
>
> /* Border color in case we don't scale up to the full screen. Black by
> * default, change to something else for debugging. */
> @@ -2195,8 +2196,8 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
>
> drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
> - intel_de_read(dev_priv, PFIT_CONTROL));
> - intel_de_write(dev_priv, PFIT_CONTROL, 0);
> + intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)));
> + intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), 0);
> }
>
> static void i9xx_crtc_disable(struct intel_atomic_state *state,
> @@ -2974,7 +2975,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
> if (!i9xx_has_pfit(dev_priv))
> return;
>
> - tmp = intel_de_read(dev_priv, PFIT_CONTROL);
> + tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv));
> if (!(tmp & PFIT_ENABLE))
> return;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index 891777481dd9..9f018503d4fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -148,7 +148,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
>
> /* gen2/3 store dither state in pfit control, needs to match */
> if (DISPLAY_VER(dev_priv) < 4) {
> - tmp = intel_de_read(dev_priv, PFIT_CONTROL);
> + tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv));
>
> crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
> index 1c2099ed5514..e41881f08d1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> @@ -950,7 +950,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
> } else {
> u32 tmp;
>
> - if (intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_VERT_AUTO_SCALE)
> + if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE)
> tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
> else
> tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 166c7f4f9c6c..b0dbe6113bbc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1588,7 +1588,7 @@
> #define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23)
>
> /* Panel fitting */
> -#define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
> +#define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
> #define PFIT_ENABLE REG_BIT(31)
> #define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */
> #define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))
> --
> 2.39.2
>
