Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_LINK_N2 register macro. Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9df8e486a86e..952780028630 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2664,7 +2664,7 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, PIPE_DATA_M2(dev_priv, transcoder), PIPE_DATA_N2(dev_priv, transcoder), PIPE_LINK_M2(dev_priv, transcoder), - PIPE_LINK_N2(transcoder)); + PIPE_LINK_N2(dev_priv, transcoder)); } static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) @@ -3364,7 +3364,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, PIPE_DATA_M2(dev_priv, transcoder), PIPE_DATA_N2(dev_priv, transcoder), PIPE_LINK_M2(dev_priv, transcoder), - PIPE_LINK_N2(transcoder)); + PIPE_LINK_N2(dev_priv, transcoder)); } static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2a73ad779e26..70e549b38984 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2386,7 +2386,7 @@ #define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) #define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2) -#define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) +#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) /* CPU panel fitter */ /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index d1a51ae042f1..955c9a33212a 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -273,7 +273,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_A)); - MMIO_D(PIPE_LINK_N2(TRANSCODER_A)); + MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B)); @@ -281,7 +281,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_B)); - MMIO_D(PIPE_LINK_N2(TRANSCODER_B)); + MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C)); @@ -289,7 +289,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_C)); - MMIO_D(PIPE_LINK_N2(TRANSCODER_C)); + MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP)); @@ -297,7 +297,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_EDP)); - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP)); + MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_EDP)); MMIO_D(PF_CTL(PIPE_A)); MMIO_D(PF_WIN_SZ(PIPE_A)); MMIO_D(PF_WIN_POS(PIPE_A)); -- 2.39.2
