Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_LINK_M1 register macro. Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_display.c | 6 ++++-- drivers/gpu/drm/i915/gvt/display.c | 4 ++-- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 5 files changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7bf5b2559143..a3249d782a8b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2643,7 +2643,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, intel_set_m_n(dev_priv, m_n, PIPE_DATA_M1(dev_priv, transcoder), PIPE_DATA_N1(dev_priv, transcoder), - PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); + PIPE_LINK_M1(dev_priv, transcoder), + PIPE_LINK_N1(transcoder)); else intel_set_m_n(dev_priv, m_n, PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), @@ -3341,7 +3342,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, intel_get_m_n(dev_priv, m_n, PIPE_DATA_M1(dev_priv, transcoder), PIPE_DATA_N1(dev_priv, transcoder), - PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); + PIPE_LINK_M1(dev_priv, transcoder), + PIPE_LINK_N1(transcoder)); else intel_get_m_n(dev_priv, m_n, PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 5f3ee57b5982..eea956603cc8 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -264,7 +264,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; - vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; + vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e; vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; /* Enable per-DDI/PORT vreg */ @@ -398,7 +398,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; - vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; + vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e; vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; } diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 88ef8b7b9ab4..ae5a3e2a5c50 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -673,7 +673,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) dp_br = skl_vgpu_get_dp_bitrate(vgpu, port); /* Get DP link symbol clock M/N */ - link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)); + link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)); link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)); /* Get H/V total from transcoder timing */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 465d73ef43e2..a9f3c4a85318 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2383,7 +2383,7 @@ #define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1) #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) -#define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) +#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) #define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) #define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2) #define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 829196c665c6..c08b8e755377 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -270,7 +270,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A)); - MMIO_D(PIPE_LINK_M1(TRANSCODER_A)); + MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_LINK_N1(TRANSCODER_A)); MMIO_D(PIPE_LINK_M2(TRANSCODER_A)); MMIO_D(PIPE_LINK_N2(TRANSCODER_A)); @@ -278,7 +278,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B)); - MMIO_D(PIPE_LINK_M1(TRANSCODER_B)); + MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_LINK_N1(TRANSCODER_B)); MMIO_D(PIPE_LINK_M2(TRANSCODER_B)); MMIO_D(PIPE_LINK_N2(TRANSCODER_B)); @@ -286,7 +286,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C)); - MMIO_D(PIPE_LINK_M1(TRANSCODER_C)); + MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_LINK_N1(TRANSCODER_C)); MMIO_D(PIPE_LINK_M2(TRANSCODER_C)); MMIO_D(PIPE_LINK_N2(TRANSCODER_C)); @@ -294,7 +294,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP)); - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP)); + MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP)); MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP)); MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP)); -- 2.39.2
