We were turning this on for ILK regardless of whether or not we use FBC.
We can save the slightest amount of power if we don't disable it when
not using FBC.
The workaround should be bit 8 for ILK. Notice it is 1 bit difference
from SNB. This is actually DPFCR unit as we've defined it.
Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 686699c..bbcf100 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -238,6 +238,11 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
SNB_CPU_FENCE_ENABLE | obj->fence_reg);
I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
sandybridge_blit_fbc_update(dev);
+ } else {
+ /* WaFbcDisableDpfcClockGating:ilk */
+ I915_WRITE(ILK_DSPCLK_GATE_D,
+ I915_READ(ILK_DSPCLK_GATE_D) |
+ ILK_DPFCRUNIT_CLOCK_GATE_DISABLE);
}
DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
@@ -254,6 +259,12 @@ static void ironlake_disable_fbc(struct drm_device *dev)
dpfc_ctl &= ~DPFC_CTL_EN;
I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
+ if (IS_GEN5(dev))
+ /* WaFbcDisableDpfcClockGating:ilk */
+ I915_WRITE(ILK_DSPCLK_GATE_D,
+ I915_READ(ILK_DSPCLK_GATE_D) &
+ ~ILK_DPFCRUNIT_CLOCK_GATE_DISABLE);
+
DRM_DEBUG_KMS("disabled FBC\n");
}
}
@@ -4932,9 +4943,9 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
/*
* Required for FBC
- * WaFbcDisableDpfcClockGating:ilk
+ * WaFbcDisableDpfcClockGating:snb
*/
- dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
+ dspclk_gate |=
ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
--
1.8.4.1
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